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https://github.com/RPCS3/llvm-mirror.git
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92f45597fa
Summary: Implements fastLowerArguments() to avoid the need to fall back on SelectionDAG for 0-4 argument functions that don't do tricky things like passing double in a pair of i32's. This allows us to move all except one test to -fast-isel-abort=3. The remaining one has function prototypes of the form 'i32 (i32, double, double)' which requires floats to be passed in GPR's. The previous commit had an uninitialized variable that caused the incoming argument region to have undefined size. This has been fixed. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D22680 llvm-svn: 277136
123 lines
4.7 KiB
LLVM
123 lines
4.7 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 \
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; RUN: -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 \
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; RUN: -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s
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@s1 = global i16 -89, align 2
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@s2 = global i16 4, align 2
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@us1 = global i16 -503, align 2
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@us2 = global i16 5, align 2
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@s3 = common global i16 0, align 2
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@us3 = common global i16 0, align 2
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define void @sll() {
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entry:
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%0 = load i16, i16* @s1, align 2
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%1 = load i16, i16* @s2, align 2
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%shl = shl i16 %0, %1
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store i16 %shl, i16* @s3, align 2
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; CHECK-LABEL: sll:
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
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; CHECK-DAG: lw $[[S2_ADDR:[0-9]+]], %got(s2)($[[REG_GP]])
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; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
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; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
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; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]])
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; CHECK: sllv $[[RES:[0-9]+]], $[[S1]], $[[S2]]
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; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
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ret void
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}
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define void @slli() {
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entry:
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%0 = load i16, i16* @s1, align 2
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%shl = shl i16 %0, 5
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store i16 %shl, i16* @s3, align 2
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; CHECK-LABEL: slli:
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
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; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
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; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
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; CHECK: sll $[[RES:[0-9]+]], $[[S1]], 5
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; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
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ret void
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}
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define void @srl() {
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entry:
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%0 = load i16, i16* @us1, align 2
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%1 = load i16, i16* @us2, align 2
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%shr = lshr i16 %0, %1
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store i16 %shr, i16* @us3, align 2
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ret void
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; CHECK-LABEL: srl:
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]])
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; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]])
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; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
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; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
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; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
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; CHECK: srlv $[[RES:[0-9]+]], $[[US1]], $[[US2]]
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; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
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}
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define void @srli() {
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entry:
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%0 = load i16, i16* @us1, align 2
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%shr = lshr i16 %0, 4
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store i16 %shr, i16* @us3, align 2
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; CHECK-LABEL: srli:
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]])
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; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
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; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
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; CHECK: srl $[[RES:[0-9]+]], $[[US1]], 4
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; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
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ret void
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}
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define void @sra() {
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entry:
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%0 = load i16, i16* @s1, align 2
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%1 = load i16, i16* @s2, align 2
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%shr = ashr i16 %0, %1
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store i16 %shr, i16* @s3, align 2
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; CHECK-LABEL: sra:
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
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; CHECK-DAG: lw $[[S2_ADDR:[0-9]+]], %got(s2)($[[REG_GP]])
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; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
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; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
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; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]])
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; CHECK: srav $[[RES:[0-9]+]], $[[S1]], $[[S2]]
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; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
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ret void
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}
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define void @srai() {
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entry:
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%0 = load i16, i16* @s1, align 2
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%shr = ashr i16 %0, 2
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store i16 %shr, i16* @s3, align 2
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; CHECK-LABEL: srai:
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]])
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; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
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; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
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; CHECK: sra $[[RES:[0-9]+]], $[[S1]], 2
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; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
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ret void
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}
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