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5c443ee383
The virtual registers are serialized using a YAML sequence of YAML inline mappings. Each mapping has the id of the virtual register and the register class. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10981 llvm-svn: 241868
27 lines
562 B
YAML
27 lines
562 B
YAML
# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
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# This test ensures that the MIR parser reports an error when it encounters an
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# unknown register class.
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--- |
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define i32 @test(i32 %a) {
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entry:
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ret i32 %a
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}
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...
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---
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name: test
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isSSA: true
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tracksRegLiveness: true
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registers:
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# CHECK: [[@LINE+1]]:20: use of undefined register class 'gr3200'
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- {id: 0, class: 'gr3200'}
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body:
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- id: 0
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name: entry
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instructions:
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- 'RETQ %eax'
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...
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