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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-24 05:23:45 +02:00
llvm-mirror/test/CodeGen
2017-04-21 19:25:33 +00:00
..
AArch64 [AArch64] Improve code generation for logical instructions taking 2017-04-21 18:53:12 +00:00
AMDGPU AMDGPU: Do not lower fast unsafe div for safe, f32, with fp32 denormals 2017-04-21 19:25:33 +00:00
ARM ARM: don't try to create an i8 -> i32 vpaddl. 2017-04-21 17:21:59 +00:00
AVR [AVR] Remove the 'multibyte' asm test 2017-04-19 12:13:45 +00:00
BPF [bpf] Fix memory offset check for loads and stores 2017-04-13 22:24:13 +00:00
Generic [Hexagon] Unxfail passing tests 2017-04-13 16:05:35 +00:00
Hexagon [Hexagon] Generate proper offset in opt-addr-mode 2017-04-19 15:15:51 +00:00
Inputs
Lanai
Mips [mips][msa] Mask vectors holding shift amounts 2017-04-20 13:26:46 +00:00
MIR MIR: Allow parsing of empty machine functions 2017-04-11 19:32:41 +00:00
MSP430
NVPTX
PowerPC [DAG] add splat vector support for 'xor' in SimplifyDemandedBits 2017-04-19 21:23:09 +00:00
SPARC
SystemZ
Thumb [Thumb1] The recently added tADCS and tSBCS pseudo-instructions were missing Uses = [CPSR] 2017-04-21 07:35:21 +00:00
Thumb2
WebAssembly [WebAssembly] Fix WebAssemblyOptimizeReturned after r300367 2017-04-17 21:40:28 +00:00
WinEH
X86 [ConstHoisting] Add BFI in constanthoisting pass and select the best insertion 2017-04-21 15:50:16 +00:00
XCore