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080cb64e9c
Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search which only checks for parallel stores
through the chain subgraph. This is cleaner as the separation of
non-interfering loads/stores from the store-merging logic.
Whem merging stores, search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited. This improves the quality of the
output SelectionDAG and generally the output CodeGen (with some
exceptions).
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the the chain aggregation in the merged stores across
code paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seemed sufficient to not cause regressions in
tests.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable. Some tests relying on the order were changed to use
volatile memory operations
Noteworthy tests:
CodeGen/AArch64/argument-blocks.ll -
It's not entirely clear what the test_varargs_stackalign test is
supposed to be asserting, but the new code looks right.
CodeGen/AArch64/arm64-memset-inline.lli -
CodeGen/AArch64/arm64-stur.ll -
CodeGen/ARM/memset-inline.ll -
The backend now generates *worse* code due to store merging
succeeding, as we do do a 16-byte constant-zero store efficiently.
CodeGen/AArch64/merge-store.ll -
Improved, but there still seems to be an extraneous vector insert
from an element to itself?
CodeGen/PowerPC/ppc64-align-long-double.ll -
Worse code emitted in this case, due to the improved store->load
forwarding.
CodeGen/X86/dag-merge-fast-accesses.ll -
CodeGen/X86/MergeConsecutiveStores.ll -
CodeGen/X86/stores-merging.ll -
CodeGen/Mips/load-store-left-right.ll -
Restored correct merging of non-aligned stores
CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll -
Improved. Correctly merges buffer_store_dword calls
CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll -
Improved. Sidesteps loading a stored value and merges two stores
CodeGen/X86/pr18023.ll -
This test has been removed, as it was asserting incorrect
behavior. Non-volatile stores *CAN* be moved past volatile loads,
and now are.
CodeGen/X86/vector-idiv.ll -
CodeGen/X86/vector-lzcnt-128.ll -
It's basically impossible to tell what these tests are actually
testing. But, looks like the code got better due to the memory
operations being recognized as non-aliasing.
CodeGen/X86/win32-eh.ll -
Both loads of the securitycookie are now merged.
CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll -
This test appears to work but no longer exhibits the spill
behavior.
Reviewers: arsenm, hfinkel, tstellarAMD, nhaehnle, jyknight
Subscribers: wdng, nhaehnle, nemanjai, arsenm, weimingz, niravd, RKSimon, aemerson, qcolombet, resistor, tstellarAMD, t.p.northover, spatel
Differential Revision: https://reviews.llvm.org/D14834
llvm-svn: 282600
102 lines
2.8 KiB
LLVM
102 lines
2.8 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
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%struct.X = type <{ i32, i64, i64 }>
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define void @foo1(i32* %p, i64 %val) nounwind {
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; CHECK-LABEL: foo1:
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; CHECK: stur w1, [x0, #-4]
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; CHECK-NEXT: ret
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%tmp1 = trunc i64 %val to i32
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%ptr = getelementptr inbounds i32, i32* %p, i64 -1
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store i32 %tmp1, i32* %ptr, align 4
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ret void
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}
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define void @foo2(i16* %p, i64 %val) nounwind {
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; CHECK-LABEL: foo2:
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; CHECK: sturh w1, [x0, #-2]
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; CHECK-NEXT: ret
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%tmp1 = trunc i64 %val to i16
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%ptr = getelementptr inbounds i16, i16* %p, i64 -1
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store i16 %tmp1, i16* %ptr, align 2
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ret void
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}
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define void @foo3(i8* %p, i64 %val) nounwind {
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; CHECK-LABEL: foo3:
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; CHECK: sturb w1, [x0, #-1]
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; CHECK-NEXT: ret
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%tmp1 = trunc i64 %val to i8
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%ptr = getelementptr inbounds i8, i8* %p, i64 -1
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store i8 %tmp1, i8* %ptr, align 1
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ret void
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}
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define void @foo4(i16* %p, i32 %val) nounwind {
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; CHECK-LABEL: foo4:
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; CHECK: sturh w1, [x0, #-2]
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; CHECK-NEXT: ret
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%tmp1 = trunc i32 %val to i16
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%ptr = getelementptr inbounds i16, i16* %p, i32 -1
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store i16 %tmp1, i16* %ptr, align 2
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ret void
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}
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define void @foo5(i8* %p, i32 %val) nounwind {
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; CHECK-LABEL: foo5:
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; CHECK: sturb w1, [x0, #-1]
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; CHECK-NEXT: ret
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%tmp1 = trunc i32 %val to i8
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%ptr = getelementptr inbounds i8, i8* %p, i32 -1
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store i8 %tmp1, i8* %ptr, align 1
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ret void
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}
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;; FIXME: Again, with the writing of a quadword zero...
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define void @foo(%struct.X* nocapture %p) nounwind optsize ssp {
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; CHECK-LABEL: foo:
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; CHECK-NOT: str
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; CHECK: stur q0, [x0, #4]
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; CHECK-FIXME: stur xzr, [x0, #12]
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; CHECK-FIXME-NEXT: stur xzr, [x0, #4]
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; CHECK-NEXT: ret
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%B = getelementptr inbounds %struct.X, %struct.X* %p, i64 0, i32 1
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%val = bitcast i64* %B to i8*
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call void @llvm.memset.p0i8.i64(i8* %val, i8 0, i64 16, i32 1, i1 false)
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ret void
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}
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
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; Unaligned 16b stores are split into 8b stores for performance.
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; radar://15424193
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; CHECK-LABEL: unaligned:
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; CHECK-NOT: str q0
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; CHECK: str d[[REG:[0-9]+]], [x0]
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; CHECK: ext.16b v[[REG2:[0-9]+]], v[[REG]], v[[REG]], #8
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; CHECK: str d[[REG2]], [x0, #8]
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define void @unaligned(<4 x i32>* %p, <4 x i32> %v) nounwind {
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store <4 x i32> %v, <4 x i32>* %p, align 4
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ret void
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}
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; CHECK-LABEL: aligned:
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; CHECK: str q0
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define void @aligned(<4 x i32>* %p, <4 x i32> %v) nounwind {
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store <4 x i32> %v, <4 x i32>* %p
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ret void
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}
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; Don't split one and two byte aligned stores.
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; radar://16349308
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; CHECK-LABEL: twobytealign:
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; CHECK: str q0
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define void @twobytealign(<4 x i32>* %p, <4 x i32> %v) nounwind {
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store <4 x i32> %v, <4 x i32>* %p, align 2
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ret void
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}
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; CHECK-LABEL: onebytealign:
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; CHECK: str q0
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define void @onebytealign(<4 x i32>* %p, <4 x i32> %v) nounwind {
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store <4 x i32> %v, <4 x i32>* %p, align 1
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ret void
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}
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