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fdc59ed6fb
And implement it for AArch64, supporting x/w ADD/OR. Differential Revision: https://reviews.llvm.org/D22373 llvm-svn: 276875
64 lines
2.4 KiB
C++
64 lines
2.4 KiB
C++
//==-- llvm/CodeGen/GlobalISel/InstructionSelector.h -------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file declares the API for the instruction selector.
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/// This class is responsible for selecting machine instructions.
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/// It's implemented by the target. It's used by the InstructionSelect pass.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
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#define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
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namespace llvm {
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class MachineInstr;
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class RegisterBankInfo;
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class TargetInstrInfo;
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class TargetRegisterInfo;
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/// Provides the logic to select generic machine instructions.
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class InstructionSelector {
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public:
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virtual ~InstructionSelector() {}
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/// Select the (possibly generic) instruction \p I to only use target-specific
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/// opcodes. It is OK to insert multiple instructions, but they cannot be
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/// generic pre-isel instructions.
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///
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/// \returns whether selection succeeded.
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/// \pre I.getParent() && I.getParent()->getParent()
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/// \post
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/// if returns true:
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/// for I in all mutated/inserted instructions:
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/// !isPreISelGenericOpcode(I.getOpcode())
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///
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virtual bool select(MachineInstr &I) const = 0;
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protected:
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InstructionSelector();
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/// Mutate the newly-selected instruction \p I to constrain its (possibly
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/// generic) virtual register operands to the instruction's register class.
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/// This could involve inserting COPYs before (for uses) or after (for defs).
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/// This requires the number of operands to match the instruction description.
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/// \returns whether operand regclass constraining succeeded.
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///
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// FIXME: Not all instructions have the same number of operands. We should
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// probably expose a constrain helper per operand and let the target selector
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// constrain individual registers, like fast-isel.
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bool constrainSelectedInstRegOperands(MachineInstr &I,
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const TargetInstrInfo &TII,
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const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) const;
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};
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} // End namespace llvm.
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#endif
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