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71647c0d9d
This is a follow-up to r325169, this time for all types, not just HVX vector types. Disable this by default, since it's not always safe. llvm-svn: 326915
32 lines
922 B
LLVM
32 lines
922 B
LLVM
; RUN: llc -march=hexagon -hexagon-align-loads=0 < %s | FileCheck %s
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; CHECK-LABEL: aligned_load:
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; CHECK: = vmem({{.*}})
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define <16 x i32> @aligned_load(<16 x i32>* %p, <16 x i32> %a) #0 {
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%v = load <16 x i32>, <16 x i32>* %p, align 64
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ret <16 x i32> %v
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}
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; CHECK-LABEL: aligned_store:
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; CHECK: vmem({{.*}}) =
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define void @aligned_store(<16 x i32>* %p, <16 x i32> %a) #0 {
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store <16 x i32> %a, <16 x i32>* %p, align 64
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ret void
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}
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; CHECK-LABEL: unaligned_load:
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; CHECK: = vmemu({{.*}})
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define <16 x i32> @unaligned_load(<16 x i32>* %p, <16 x i32> %a) #0 {
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%v = load <16 x i32>, <16 x i32>* %p, align 32
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ret <16 x i32> %v
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}
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; CHECK-LABEL: unaligned_store:
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; CHECK: vmemu({{.*}}) =
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define void @unaligned_store(<16 x i32>* %p, <16 x i32> %a) #0 {
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store <16 x i32> %a, <16 x i32>* %p, align 32
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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