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77cd5c40d2
This is the groundwork for Armv8.2-A FP16 code generation .
Clang passes and returns _Float16 values as floats, together with the required
bitconverts and truncs etc. to implement correct AAPCS behaviour, see D42318.
We will implement half-precision argument passing/returning lowering in the ARM
backend soon, but for now this means that this:
_Float16 sub(_Float16 a, _Float16 b) {
return a + b;
}
gets lowered to this:
define float @sub(float %a.coerce, float %b.coerce) {
entry:
%0 = bitcast float %a.coerce to i32
%tmp.0.extract.trunc = trunc i32 %0 to i16
%1 = bitcast i16 %tmp.0.extract.trunc to half
<SNIP>
%add = fadd half %1, %3
<SNIP>
}
When FullFP16 is *not* supported, we don't make f16 a legal type, and we get
legalization for "free", i.e. nothing changes and everything works as before.
And also f16 argument passing/returning is handled.
When FullFP16 is supported, we do make f16 a legal type, and have 2 places that
we need to patch up: f16 argument passing and returning, which involves minor
tweaks to avoid unnecessary code generation for some bitcasts.
As a "demonstrator" that this works for the different FP16, FullFP16, softfp
modes, etc., I've added match rules to the VSUB instruction description showing
that we can codegen this instruction from IR, but more importantly, also to
some conversion instructions. These conversions were causing issue before in
the FP16 and FullFP16 cases.
I've also added match rules to the VLDRH and VSTRH desriptions, so that we can
actually compile the entire half-precision sub code example above. This showed
that these loads and stores had the wrong addressing mode specified: AddrMode5
instead of AddrMode5FP16, which turned out not be implemented at all, so that
has also been added.
This is the minimal patch that shows all the different moving parts. In patch
2/3 I will add some efficient lowering of bitcasts, and in 2/3 I will add the
remaining Armv8.2-A FP16 instruction descriptions.
Thanks to Sam Parker and Oliver Stannard for their help and reviews!
Differential Revision: https://reviews.llvm.org/D38315
llvm-svn: 323512
482 lines
20 KiB
TableGen
482 lines
20 KiB
TableGen
//===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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include "ARMSystemRegister.td"
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//===----------------------------------------------------------------------===//
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// Declarations that describe the ARM register file
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//===----------------------------------------------------------------------===//
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// Registers are identified with 4-bit ID numbers.
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class ARMReg<bits<16> Enc, string n, list<Register> subregs = []> : Register<n> {
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let HWEncoding = Enc;
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let Namespace = "ARM";
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let SubRegs = subregs;
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// All bits of ARM registers with sub-registers are covered by sub-registers.
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let CoveredBySubRegs = 1;
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}
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class ARMFReg<bits<16> Enc, string n> : Register<n> {
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let HWEncoding = Enc;
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let Namespace = "ARM";
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}
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// Subregister indices.
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let Namespace = "ARM" in {
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def qqsub_0 : SubRegIndex<256>;
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def qqsub_1 : SubRegIndex<256, 256>;
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// Note: Code depends on these having consecutive numbers.
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def qsub_0 : SubRegIndex<128>;
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def qsub_1 : SubRegIndex<128, 128>;
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def qsub_2 : ComposedSubRegIndex<qqsub_1, qsub_0>;
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def qsub_3 : ComposedSubRegIndex<qqsub_1, qsub_1>;
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def dsub_0 : SubRegIndex<64>;
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def dsub_1 : SubRegIndex<64, 64>;
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def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>;
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def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>;
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def dsub_4 : ComposedSubRegIndex<qsub_2, dsub_0>;
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def dsub_5 : ComposedSubRegIndex<qsub_2, dsub_1>;
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def dsub_6 : ComposedSubRegIndex<qsub_3, dsub_0>;
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def dsub_7 : ComposedSubRegIndex<qsub_3, dsub_1>;
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def ssub_0 : SubRegIndex<32>;
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def ssub_1 : SubRegIndex<32, 32>;
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def ssub_2 : ComposedSubRegIndex<dsub_1, ssub_0>;
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def ssub_3 : ComposedSubRegIndex<dsub_1, ssub_1>;
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def ssub_4 : ComposedSubRegIndex<dsub_2, ssub_0>;
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def ssub_5 : ComposedSubRegIndex<dsub_2, ssub_1>;
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def ssub_6 : ComposedSubRegIndex<dsub_3, ssub_0>;
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def ssub_7 : ComposedSubRegIndex<dsub_3, ssub_1>;
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def ssub_8 : ComposedSubRegIndex<dsub_4, ssub_0>;
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def ssub_9 : ComposedSubRegIndex<dsub_4, ssub_1>;
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def ssub_10 : ComposedSubRegIndex<dsub_5, ssub_0>;
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def ssub_11 : ComposedSubRegIndex<dsub_5, ssub_1>;
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def ssub_12 : ComposedSubRegIndex<dsub_6, ssub_0>;
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def ssub_13 : ComposedSubRegIndex<dsub_6, ssub_1>;
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def gsub_0 : SubRegIndex<32>;
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def gsub_1 : SubRegIndex<32, 32>;
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// Let TableGen synthesize the remaining 12 ssub_* indices.
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// We don't need to name them.
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}
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// Integer registers
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def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
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def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
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def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
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def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
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def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
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def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
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def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
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def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
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// These require 32-bit instructions.
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let CostPerUse = 1 in {
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def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
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def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
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def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
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def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
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def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
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def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>;
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def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
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def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>;
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}
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// Float registers
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def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">;
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def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">;
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def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">;
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def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">;
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def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">;
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def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">;
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def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
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def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;
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def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;
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def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">;
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def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
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def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">;
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def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
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def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
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def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
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def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
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// Aliases of the F* registers used to hold 64-bit fp values (doubles)
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let SubRegIndices = [ssub_0, ssub_1] in {
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def D0 : ARMReg< 0, "d0", [S0, S1]>, DwarfRegNum<[256]>;
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def D1 : ARMReg< 1, "d1", [S2, S3]>, DwarfRegNum<[257]>;
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def D2 : ARMReg< 2, "d2", [S4, S5]>, DwarfRegNum<[258]>;
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def D3 : ARMReg< 3, "d3", [S6, S7]>, DwarfRegNum<[259]>;
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def D4 : ARMReg< 4, "d4", [S8, S9]>, DwarfRegNum<[260]>;
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def D5 : ARMReg< 5, "d5", [S10, S11]>, DwarfRegNum<[261]>;
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def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>;
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def D7 : ARMReg< 7, "d7", [S14, S15]>, DwarfRegNum<[263]>;
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def D8 : ARMReg< 8, "d8", [S16, S17]>, DwarfRegNum<[264]>;
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def D9 : ARMReg< 9, "d9", [S18, S19]>, DwarfRegNum<[265]>;
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def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;
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def D11 : ARMReg<11, "d11", [S22, S23]>, DwarfRegNum<[267]>;
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def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>;
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def D13 : ARMReg<13, "d13", [S26, S27]>, DwarfRegNum<[269]>;
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def D14 : ARMReg<14, "d14", [S28, S29]>, DwarfRegNum<[270]>;
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def D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>;
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}
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// VFP3 defines 16 additional double registers
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def D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>;
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def D17 : ARMFReg<17, "d17">, DwarfRegNum<[273]>;
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def D18 : ARMFReg<18, "d18">, DwarfRegNum<[274]>;
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def D19 : ARMFReg<19, "d19">, DwarfRegNum<[275]>;
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def D20 : ARMFReg<20, "d20">, DwarfRegNum<[276]>;
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def D21 : ARMFReg<21, "d21">, DwarfRegNum<[277]>;
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def D22 : ARMFReg<22, "d22">, DwarfRegNum<[278]>;
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def D23 : ARMFReg<23, "d23">, DwarfRegNum<[279]>;
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def D24 : ARMFReg<24, "d24">, DwarfRegNum<[280]>;
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def D25 : ARMFReg<25, "d25">, DwarfRegNum<[281]>;
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def D26 : ARMFReg<26, "d26">, DwarfRegNum<[282]>;
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def D27 : ARMFReg<27, "d27">, DwarfRegNum<[283]>;
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def D28 : ARMFReg<28, "d28">, DwarfRegNum<[284]>;
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def D29 : ARMFReg<29, "d29">, DwarfRegNum<[285]>;
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def D30 : ARMFReg<30, "d30">, DwarfRegNum<[286]>;
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def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>;
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// Advanced SIMD (NEON) defines 16 quad-word aliases
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let SubRegIndices = [dsub_0, dsub_1] in {
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def Q0 : ARMReg< 0, "q0", [D0, D1]>;
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def Q1 : ARMReg< 1, "q1", [D2, D3]>;
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def Q2 : ARMReg< 2, "q2", [D4, D5]>;
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def Q3 : ARMReg< 3, "q3", [D6, D7]>;
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def Q4 : ARMReg< 4, "q4", [D8, D9]>;
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def Q5 : ARMReg< 5, "q5", [D10, D11]>;
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def Q6 : ARMReg< 6, "q6", [D12, D13]>;
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def Q7 : ARMReg< 7, "q7", [D14, D15]>;
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}
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let SubRegIndices = [dsub_0, dsub_1] in {
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def Q8 : ARMReg< 8, "q8", [D16, D17]>;
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def Q9 : ARMReg< 9, "q9", [D18, D19]>;
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def Q10 : ARMReg<10, "q10", [D20, D21]>;
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def Q11 : ARMReg<11, "q11", [D22, D23]>;
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def Q12 : ARMReg<12, "q12", [D24, D25]>;
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def Q13 : ARMReg<13, "q13", [D26, D27]>;
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def Q14 : ARMReg<14, "q14", [D28, D29]>;
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def Q15 : ARMReg<15, "q15", [D30, D31]>;
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}
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// Current Program Status Register.
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// We model fpscr with two registers: FPSCR models the control bits and will be
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// reserved. FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV
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// models the APSR when it's accessed by some special instructions. In such cases
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// it has the same encoding as PC.
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def CPSR : ARMReg<0, "cpsr">;
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def APSR : ARMReg<1, "apsr">;
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def APSR_NZCV : ARMReg<15, "apsr_nzcv">;
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def SPSR : ARMReg<2, "spsr">;
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def FPSCR : ARMReg<3, "fpscr">;
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def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> {
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let Aliases = [FPSCR];
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}
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def ITSTATE : ARMReg<4, "itstate">;
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// Special Registers - only available in privileged mode.
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def FPSID : ARMReg<0, "fpsid">;
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def MVFR2 : ARMReg<5, "mvfr2">;
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def MVFR1 : ARMReg<6, "mvfr1">;
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def MVFR0 : ARMReg<7, "mvfr0">;
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def FPEXC : ARMReg<8, "fpexc">;
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def FPINST : ARMReg<9, "fpinst">;
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def FPINST2 : ARMReg<10, "fpinst2">;
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// Register classes.
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//
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// pc == Program Counter
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// lr == Link Register
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// sp == Stack Pointer
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// r12 == ip (scratch)
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// r7 == Frame Pointer (thumb-style backtraces)
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// r9 == May be reserved as Thread Register
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// r11 == Frame Pointer (arm-style backtraces)
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// r10 == Stack Limit
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//
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def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
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SP, LR, PC)> {
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// Allocate LR as the first CSR since it is always saved anyway.
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// For Thumb1 mode, we don't want to allocate hi regs at all, as we don't
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// know how to spill them. If we make our prologue/epilogue code smarter at
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// some point, we can go back to using the above allocation orders for the
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// Thumb1 instructions that know how to use hi regs.
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let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
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let AltOrderSelect = [{
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return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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let DiagnosticString = "operand must be a register in range [r0, r15]";
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}
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// GPRs without the PC. Some ARM instructions do not allow the PC in
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// certain operand slots, particularly as the destination. Primarily
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// useful for disassembly.
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def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
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let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
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let AltOrderSelect = [{
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return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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let DiagnosticString = "operand must be a register in range [r0, r14]";
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}
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// GPRs without the PC but with APSR. Some instructions allow accessing the
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// APSR, while actually encoding PC in the register field. This is useful
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// for assembly and disassembly only.
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def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
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let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
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let AltOrderSelect = [{
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return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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let DiagnosticString = "operand must be a register in range [r0, r14] or apsr_nzcv";
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}
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// GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the
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// implied SP argument list.
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// FIXME: It would be better to not use this at all and refactor the
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// instructions to not have SP an an explicit argument. That makes
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// frame index resolution a bit trickier, though.
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def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)> {
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let DiagnosticString = "operand must be a register sp";
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}
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// restricted GPR register class. Many Thumb2 instructions allow the full
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// register range for operands, but have undefined behaviours when PC
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// or SP (R13 or R15) are used. The ARM ISA refers to these operands
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// via the BadReg() pseudo-code description.
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def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
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let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
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let AltOrderSelect = [{
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return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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let DiagnosticType = "rGPR";
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}
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// Thumb registers are R0-R7 normally. Some instructions can still use
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// the general GPR register class above (MOV, e.g.)
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def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> {
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let DiagnosticString = "operand must be a register in range [r0, r7]";
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}
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// Thumb registers R0-R7 and the PC. Some instructions like TBB or THH allow
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// the PC to be used as a destination operand as well.
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def tGPRwithpc : RegisterClass<"ARM", [i32], 32, (add tGPR, PC)>;
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// The high registers in thumb mode, R8-R15.
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def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)> {
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let DiagnosticString = "operand must be a register in range [r8, r15]";
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}
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// For tail calls, we can't use callee-saved registers, as they are restored
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// to the saved value before the tail call, which would clobber a call address.
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// Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of
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// this class and the preceding one(!) This is what we want.
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def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
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let AltOrders = [(and tcGPR, tGPR)];
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let AltOrderSelect = [{
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return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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}
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// Condition code registers.
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def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
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let CopyCost = -1; // Don't allow copying of status registers.
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let isAllocatable = 0;
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}
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// Scalar single precision floating point register class..
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// FIXME: Allocation order changed to s0, s2, ... or s0, s4, ... as a quick hack
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// to avoid partial-write dependencies on D or Q (depending on platform)
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// registers (S registers are renamed as portions of D/Q registers).
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def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
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let AltOrders = [(add (decimate SPR, 2), SPR),
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(add (decimate SPR, 4),
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(decimate SPR, 2),
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(decimate (rotl SPR, 1), 4),
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(decimate (rotl SPR, 1), 2))];
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let AltOrderSelect = [{
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return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
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}];
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let DiagnosticString = "operand must be a register in range [s0, s31]";
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}
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def HPR : RegisterClass<"ARM", [f16], 32, (sequence "S%u", 0, 31)> {
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let AltOrders = [(add (decimate HPR, 2), SPR),
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(add (decimate HPR, 4),
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(decimate HPR, 2),
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(decimate (rotl HPR, 1), 4),
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(decimate (rotl HPR, 1), 2))];
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let AltOrderSelect = [{
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return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
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}];
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let DiagnosticString = "operand must be a register in range [s0, s31]";
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}
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// Subset of SPR which can be used as a source of NEON scalars for 16-bit
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// operations
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def SPR_8 : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 15)> {
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let DiagnosticString = "operand must be a register in range [s0, s15]";
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}
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// Scalar double precision floating point / generic 64-bit vector register
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// class.
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// ARM requires only word alignment for double. It's more performant if it
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// is double-word alignment though.
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def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
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(sequence "D%u", 0, 31)> {
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// Allocate non-VFP2 registers D16-D31 first, and prefer even registers on
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// Darwin platforms.
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let AltOrders = [(rotl DPR, 16),
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(add (decimate (rotl DPR, 16), 2), (rotl DPR, 16))];
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let AltOrderSelect = [{
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return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
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}];
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let DiagnosticType = "DPR";
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}
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// Subset of DPR that are accessible with VFP2 (and so that also have
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// 32-bit SPR subregs).
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def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
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(trunc DPR, 16)> {
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let DiagnosticString = "operand must be a register in range [d0, d15]";
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}
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// Subset of DPR which can be used as a source of NEON scalars for 16-bit
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// operations
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def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
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(trunc DPR, 8)> {
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let DiagnosticString = "operand must be a register in range [d0, d7]";
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}
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// Generic 128-bit vector register class.
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def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128,
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(sequence "Q%u", 0, 15)> {
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// Allocate non-VFP2 aliases Q8-Q15 first.
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let AltOrders = [(rotl QPR, 8)];
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let AltOrderSelect = [{ return 1; }];
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let DiagnosticString = "operand must be a register in range [q0, q15]";
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}
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// Subset of QPR that have 32-bit SPR subregs.
|
|
def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
|
128, (trunc QPR, 8)> {
|
|
let DiagnosticString = "operand must be a register in range [q0, q7]";
|
|
}
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|
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// Subset of QPR that have DPR_8 and SPR_8 subregs.
|
|
def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
|
128, (trunc QPR, 4)> {
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let DiagnosticString = "operand must be a register in range [q0, q3]";
|
|
}
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|
|
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// Pseudo-registers representing odd-even pairs of D registers. The even-odd
|
|
// pairs are already represented by the Q registers.
|
|
// These are needed by NEON instructions requiring two consecutive D registers.
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|
// There is no D31_D0 register as that is always an UNPREDICTABLE encoding.
|
|
def TuplesOE2D : RegisterTuples<[dsub_0, dsub_1],
|
|
[(decimate (shl DPR, 1), 2),
|
|
(decimate (shl DPR, 2), 2)]>;
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|
|
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// Register class representing a pair of consecutive D registers.
|
|
// Use the Q registers for the even-odd pairs.
|
|
def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
|
128, (interleave QPR, TuplesOE2D)> {
|
|
// Allocate starting at non-VFP2 registers D16-D31 first.
|
|
// Prefer even-odd pairs as they are easier to copy.
|
|
let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))];
|
|
let AltOrderSelect = [{ return 1; }];
|
|
}
|
|
|
|
// Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
|
|
// These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.
|
|
def Tuples2R : RegisterTuples<[gsub_0, gsub_1],
|
|
[(add R0, R2, R4, R6, R8, R10, R12),
|
|
(add R1, R3, R5, R7, R9, R11, SP)]>;
|
|
|
|
// Register class representing a pair of even-odd GPRs.
|
|
def GPRPair : RegisterClass<"ARM", [untyped], 64, (add Tuples2R)> {
|
|
let Size = 64; // 2 x 32 bits, we have no predefined type of that size.
|
|
}
|
|
|
|
// Pseudo-registers representing 3 consecutive D registers.
|
|
def Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2],
|
|
[(shl DPR, 0),
|
|
(shl DPR, 1),
|
|
(shl DPR, 2)]>;
|
|
|
|
// 3 consecutive D registers.
|
|
def DTriple : RegisterClass<"ARM", [untyped], 64, (add Tuples3D)> {
|
|
let Size = 192; // 3 x 64 bits, we have no predefined type of that size.
|
|
}
|
|
|
|
// Pseudo 256-bit registers to represent pairs of Q registers. These should
|
|
// never be present in the emitted code.
|
|
// These are used for NEON load / store instructions, e.g., vld4, vst3.
|
|
def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>;
|
|
|
|
// Pseudo 256-bit vector register class to model pairs of Q registers
|
|
// (4 consecutive D registers).
|
|
def QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> {
|
|
// Allocate non-VFP2 aliases first.
|
|
let AltOrders = [(rotl QQPR, 8)];
|
|
let AltOrderSelect = [{ return 1; }];
|
|
}
|
|
|
|
// Tuples of 4 D regs that isn't also a pair of Q regs.
|
|
def TuplesOE4D : RegisterTuples<[dsub_0, dsub_1, dsub_2, dsub_3],
|
|
[(decimate (shl DPR, 1), 2),
|
|
(decimate (shl DPR, 2), 2),
|
|
(decimate (shl DPR, 3), 2),
|
|
(decimate (shl DPR, 4), 2)]>;
|
|
|
|
// 4 consecutive D registers.
|
|
def DQuad : RegisterClass<"ARM", [v4i64], 256,
|
|
(interleave Tuples2Q, TuplesOE4D)>;
|
|
|
|
// Pseudo 512-bit registers to represent four consecutive Q registers.
|
|
def Tuples2QQ : RegisterTuples<[qqsub_0, qqsub_1],
|
|
[(shl QQPR, 0), (shl QQPR, 2)]>;
|
|
|
|
// Pseudo 512-bit vector register class to model 4 consecutive Q registers
|
|
// (8 consecutive D registers).
|
|
def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> {
|
|
// Allocate non-VFP2 aliases first.
|
|
let AltOrders = [(rotl QQQQPR, 8)];
|
|
let AltOrderSelect = [{ return 1; }];
|
|
}
|
|
|
|
|
|
// Pseudo-registers representing 2-spaced consecutive D registers.
|
|
def Tuples2DSpc : RegisterTuples<[dsub_0, dsub_2],
|
|
[(shl DPR, 0),
|
|
(shl DPR, 2)]>;
|
|
|
|
// Spaced pairs of D registers.
|
|
def DPairSpc : RegisterClass<"ARM", [v2i64], 64, (add Tuples2DSpc)>;
|
|
|
|
def Tuples3DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4],
|
|
[(shl DPR, 0),
|
|
(shl DPR, 2),
|
|
(shl DPR, 4)]>;
|
|
|
|
// Spaced triples of D registers.
|
|
def DTripleSpc : RegisterClass<"ARM", [untyped], 64, (add Tuples3DSpc)> {
|
|
let Size = 192; // 3 x 64 bits, we have no predefined type of that size.
|
|
}
|
|
|
|
def Tuples4DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4, dsub_6],
|
|
[(shl DPR, 0),
|
|
(shl DPR, 2),
|
|
(shl DPR, 4),
|
|
(shl DPR, 6)]>;
|
|
|
|
// Spaced quads of D registers.
|
|
def DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>;
|