James Molloy 08b726e6d4 [DemandedBits] Revert r249687 due to PR26071 ... This regresses a test in LoopVectorize, so I'll need to go away and think about how to solve this in a way that isn't broken. From the writeup in PR26071: What's happening is that ComputeKnownZeroes is telling us that all bits except the LSB are zero. We're then deciding that only the LSB needs to be demanded from the icmp's inputs. This is where we're wrong - we're assuming that after simplification the bits that were known zero will continue to be known zero. But they're not - during trivialization the upper bits get changed (because an XOR isn't shrunk), so the icmp fails. The fault is in demandedbits - its contract does clearly state that a non-demanded bit may either be zero or one. llvm-svn: 259649		2016-02-03 15:05:06 +00:00
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aarch64-unroll.ll	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
arbitrary-induction-step.ll	[AArch64] Turn on by default interleaved access vectorization	2015-09-01 11:26:46 +00:00
arm64-unroll.ll	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
deterministic-type-shrinkage.ll	[LoopVectorize] Use MapVector rather than DenseMap for MinBWs.	2015-11-26 20:39:51 +00:00
gather-cost.ll	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
interleaved_cost.ll	[AArch64] Turn on by default interleaved access vectorization	2015-09-01 11:26:46 +00:00
lit.local.cfg	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
loop-vectorization-factors.ll	[DemandedBits] Revert r249687 due to PR26071	2016-02-03 15:05:06 +00:00
reduction-small-size.ll	[LV] Relax Small Size Reduction Type Requirement	2015-09-10 21:12:57 +00:00
sdiv-pow2.ll	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00