Matt Arsenault 43f82fec05 AMDGPU/GlobalISel: Start selectively legalizing 16-bit operations ... It might be a bit nicer to use the fancy .legalIf and co. predicates, but this was requiring more boilerplate and disables the coverage assertions. llvm-svn: 351886		2019-01-22 22:00:19 +00:00
..
AArch64	GlobalISel: Allow shift amount to be a different type	2019-01-22 21:42:11 +00:00
AMDGPU	AMDGPU/GlobalISel: Start selectively legalizing 16-bit operations	2019-01-22 22:00:19 +00:00
ARC
ARM	[ARM GlobalISel] Allow calls to varargs functions	2019-01-17 10:11:55 +00:00
AVR	[AVR] Insert unconditional branch when inserting MBBs between blocks with fallthrough	2019-01-21 04:32:02 +00:00
BPF
Generic	[AVR] Remove unneeded XFAILs from the Generic CodeGen tests	2019-01-20 11:16:58 +00:00
Hexagon
Inputs
Lanai
Mips	[mips] Emit .reloc R_{MICRO}MIPS_JALR along with j(al)r(c) $25	2019-01-17 21:50:37 +00:00
MIR	Revert r351584: "GlobalISel: Verify g_zextload and g_sextload"	2019-01-19 00:36:11 +00:00
MSP430	[MSP430] Emit a separate section for every interrupt vector	2019-01-16 14:03:41 +00:00
NVPTX
PowerPC
RISCV	[RISCV] Quick fix for PR40333	2019-01-22 12:11:53 +00:00
SPARC
SystemZ
Thumb	[ARM] Combine ands+lsls to lsls+lsrs for Thumb1.	2019-01-22 01:51:37 +00:00
Thumb2
WebAssembly	[WebAssembly] Add languages from debug info to producers section	2019-01-18 02:47:48 +00:00
WinCFGuard
WinEH
X86	GlobalISel: Allow shift amount to be a different type	2019-01-22 21:42:11 +00:00
XCore