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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
38 lines
996 B
YAML
38 lines
996 B
YAML
# RUN: llc -march=hexagon -mcpu=hexagonv60 -run-pass post-RA-sched -o - %s | FileCheck %s
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# The post-RA scheduler reorders S2_lsr_r_p and S2_lsr_r_p_or. Both of them
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# use r9, and the last of the two kills it. The kill flag fixup did not
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# correctly update the flag, resulting in both instructions killing r9.
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# CHECK-LABEL: name: foo
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# Check for no-kill of r9 in the first instruction, after reordering:
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# CHECK: $d7 = S2_lsr_r_p_or killed $d7, killed $d1, $r9
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# CHECK: $d13 = S2_lsr_r_p killed $d0, killed $r9
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--- |
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define void @foo() {
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ret void
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}
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...
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---
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name: foo
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1
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liveins: $d0, $d1, $r9, $r13
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$d7 = S2_asl_r_p $d0, $r13
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$d5 = S2_asl_r_p $d1, killed $r13
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$d6 = S2_lsr_r_p killed $d0, $r9
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$d7 = S2_lsr_r_p_or killed $d7, killed $d1, killed $r9
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$d1 = A2_combinew killed $r11, killed $r10
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$d0 = A2_combinew killed $r15, killed $r14
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J2_jump %bb.1, implicit-def $pc
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bb.1:
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A2_nop
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...
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