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49 lines
1.4 KiB
LLVM
49 lines
1.4 KiB
LLVM
; RUN: llc -march=hexagon -enable-pipeliner < %s
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; REQUIRES: asserts
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; Check that the dependences are order correctly, and the list can be
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; updated when the instruction to insert has a def and use conflict.
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; Function Attrs: nounwind
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define fastcc void @f0() #0 {
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b0:
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br i1 undef, label %b7, label %b1
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b1: ; preds = %b0
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br i1 undef, label %b2, label %b4
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b2: ; preds = %b1
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%v0 = load i16, i16* undef, align 2
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br label %b5
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b3: ; preds = %b5
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br label %b4
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b4: ; preds = %b3, %b1
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%v1 = phi i16 [ %v11, %b3 ], [ 0, %b1 ]
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br i1 false, label %b7, label %b6
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b5: ; preds = %b5, %b2
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%v2 = phi i16 [ %v3, %b5 ], [ undef, %b2 ]
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%v3 = phi i16 [ 0, %b5 ], [ %v0, %b2 ]
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%v4 = phi i16 [ %v2, %b5 ], [ undef, %b2 ]
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%v5 = phi i16 [ %v11, %b5 ], [ 0, %b2 ]
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%v6 = phi i32 [ %v12, %b5 ], [ undef, %b2 ]
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%v7 = or i16 0, %v5
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%v8 = lshr i16 %v4, 8
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%v9 = or i16 %v8, %v7
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%v10 = or i16 0, %v9
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%v11 = or i16 0, %v10
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%v12 = add nsw i32 %v6, -32
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%v13 = icmp sgt i32 %v12, 31
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br i1 %v13, label %b5, label %b3
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b6: ; preds = %b4
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br label %b7
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b7: ; preds = %b6, %b4, %b0
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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