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llvm-mirror/test/CodeGen/ARM/dwarf-unwind.ll
Oliver Stannard 930aaa18e9 [ARM] Generate consistent frame records for Thumb2
There is not an official documented ABI for frame pointers in Thumb2,
but we should try to emit something which is useful.

We use r7 as the frame pointer for Thumb code, which currently means
that if a function needs to save a high register (r8-r11), it will get
pushed to the stack between the frame pointer (r7) and link register
(r14). This means that while a stack unwinder can follow the chain of
frame pointers up the stack, it cannot know the offset to lr, so does
not know which functions correspond to the stack frames.

To fix this, we need to push the callee-saved registers in two batches,
with the first push saving the low registers, fp and lr, and the second
push saving the high registers. This is already implemented, but
previously only used for iOS. This patch turns it on for all Thumb2
targets when frame pointers are required by the ABI, and the frame
pointer is r7 (Windows uses r11, so this isn't a problem there). If
frame pointer elimination is enabled we still emit a single push/pop
even if we need a frame pointer for other reasons, to avoid increasing
code size.

We must also ensure that lr is pushed to the stack when using a frame
pointer, so that we end up with a complete frame record. Situations that
could cause this were rare, because we already push lr in most
situations so that we can return using the pop instruction.

Differential Revision: https://reviews.llvm.org/D23516

llvm-svn: 279506
2016-08-23 09:19:22 +00:00

85 lines
2.7 KiB
LLVM

; RUN: llc -mtriple=thumbv7-netbsd-eabi -o - %s | FileCheck %s
declare void @bar()
; ARM's frame lowering attempts to tack another callee-saved register onto the
; list when it detects a potential misaligned VFP store. However, if there are
; none available it used to just vpush anyway and misreport the location of the
; registers in unwind info. Since there are benefits to aligned stores, it's
; better to correct the code than the .cfi_offset directive.
define void @test_dpr_align(i8 %l, i8 %r) {
; CHECK-LABEL: test_dpr_align:
; CHECK: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK: .cfi_def_cfa_offset 36
; CHECK: sub sp, #4
; CHECK: .cfi_def_cfa_offset 40
; CHECK: vpush {d8}
; CHECK: .cfi_offset d8, -48
; CHECK-NOT: sub sp
; [...]
; CHECK: bl bar
; CHECK-NOT: add sp
; CHECK: vpop {d8}
; CHECK: add sp, #4
; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"()
call void @bar()
ret void
}
; The prologue (but not the epilogue) can be made more space efficient by
; chucking an argument register into the list. Not worth it in general though,
; "sub sp, #4" is likely faster.
define void @test_dpr_align_tiny(i8 %l, i8 %r) minsize {
; CHECK-LABEL: test_dpr_align_tiny:
; CHECK: push.w {r3, r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NOT: sub sp
; CHECK: vpush {d8}
; CHECK: .cfi_offset d8, -48
; CHECK-NOT: sub sp
; [...]
; CHECK: bl bar
; CHECK-NOT: add sp
; CHECK: vpop {d8}
; CHECK: add sp, #4
; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"()
call void @bar()
ret void
}
; However, we shouldn't do a 2-step align/adjust if there are no DPRs to be
; saved.
define void @test_nodpr_noalign(i8 %l, i8 %r) {
; CHECK-LABEL: test_nodpr_noalign:
; CHECK: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NOT: sub sp
; CHECK: sub sp, #12
; CHECK-NOT: sub sp
; [...]
; CHECK: bl bar
; CHECK-NOT: add sp
; CHECK: add sp, #12
; CHECK-NOT: add sp
; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
alloca i64
call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"()
call void @bar()
ret void
}
define void @test_frame_pointer_offset() minsize "no-frame-pointer-elim"="true" {
; CHECK-LABEL: test_frame_pointer_offset:
; CHECK: push {r4, r5, r6, r7, lr}
; CHECK: .cfi_def_cfa_offset 20
; CHECK: add r7, sp, #12
; CHECK: .cfi_def_cfa r7, 8
; CHECK-NOT: .cfi_def_cfa_offset
; CHECK: push.w {r7, r8, r9, r10, r11}
; CHECK-NOT: .cfi_def_cfa_offset
call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"()
call void @bar()
ret void
}