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9190dc4f73
As outlined in the PR, we didn't ensure that displacements for DQ-Form instructions are multiples of 16. Since the instruction encoding encodes a quad-word displacement, a sub-16 byte displacement is meaningless and ends up being encoded incorrectly. Fixes https://bugs.llvm.org/show_bug.cgi?id=33671. Differential Revision: https://reviews.llvm.org/D35007 llvm-svn: 307934
33 lines
1.1 KiB
LLVM
33 lines
1.1 KiB
LLVM
; Function Attrs: norecurse nounwind
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; RUN: llc -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 < %s | FileCheck %s
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define void @test1(i32* nocapture readonly %arr, i32* nocapture %arrTo) {
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 4
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%0 = bitcast i32* %arrayidx to <4 x i32>*
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%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 4
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%1 = bitcast i32* %arrayidx1 to <4 x i32>*
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%2 = load <4 x i32>, <4 x i32>* %1, align 16
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store <4 x i32> %2, <4 x i32>* %0, align 16
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ret void
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; CHECK-LABEL: test1
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; CHECK: lxv [[LD:[0-9]+]], 16(3)
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; CHECK: stxv [[LD]], 16(4)
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}
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; Function Attrs: norecurse nounwind
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define void @test2(i32* nocapture readonly %arr, i32* nocapture %arrTo) {
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1
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%0 = bitcast i32* %arrayidx to <4 x i32>*
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%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
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%1 = bitcast i32* %arrayidx1 to <4 x i32>*
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%2 = load <4 x i32>, <4 x i32>* %1, align 16
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store <4 x i32> %2, <4 x i32>* %0, align 16
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ret void
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; CHECK-LABEL: test2
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; CHECK: addi 3, 3, 8
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; CHECK: lxvx [[LD:[0-9]+]], 0, 3
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; CHECK: addi 3, 4, 4
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; CHECK: stxvx [[LD]], 0, 3
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}
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