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46d19bc0c7
If the arch is P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e. y = add imm, reg LFDX. 0, y --> LFD imm(reg) Reviewers: Nemanjai Differential Revision: https://reviews.llvm.org/D49007 llvm-svn: 340149
85 lines
2.0 KiB
LLVM
85 lines
2.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-P7
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
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define signext i32 @f32toi32(float %a) {
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entry:
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%0 = bitcast float %a to i32
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ret i32 %0
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; CHECK-P7: stfs 1,
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; CHECK-P7: lwa 3,
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; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
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; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
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; CHECK: mfvsrwz 3, [[SHIFTREG]]
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}
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define i64 @f64toi64(double %a) {
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entry:
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%0 = bitcast double %a to i64
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ret i64 %0
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; CHECK-P7: stfd 1,
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; CHECK-P7: ld 3,
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; CHECK: mffprd 3, 1
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}
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define float @i32tof32(i32 signext %a) {
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entry:
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%0 = bitcast i32 %a to float
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ret float %0
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; CHECK-P7: stw 3,
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; CHECK-P7: lfs 1,
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; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3
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; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1
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; CHECK: xscvspdpn 1, [[SHIFTREG]]
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}
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define double @i64tof64(i64 %a) {
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entry:
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%0 = bitcast i64 %a to double
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ret double %0
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; CHECK-P7: std 3,
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; CHECK-P7: lfd 1,
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; CHECK: mtvsrd 1, 3
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}
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define zeroext i32 @f32toi32u(float %a) {
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entry:
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%0 = bitcast float %a to i32
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ret i32 %0
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; CHECK-P7: stfs 1,
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; CHECK-P7: lwz 3,
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; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
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; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
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; CHECK: mfvsrwz 3, [[SHIFTREG]]
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}
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define i64 @f64toi64u(double %a) {
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entry:
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%0 = bitcast double %a to i64
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ret i64 %0
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; CHECK-P7: stfd 1,
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; CHECK-P7: ld 3,
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; CHECK: mffprd 3, 1
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}
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define float @i32utof32(i32 zeroext %a) {
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entry:
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%0 = bitcast i32 %a to float
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ret float %0
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; CHECK-P7: stw 3,
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; CHECK-P7: lfs 1,
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; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3
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; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1
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; CHECK: xscvspdpn 1, [[SHIFTREG]]
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}
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define double @i64utof64(i64 %a) {
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entry:
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%0 = bitcast i64 %a to double
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ret double %0
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; CHECK-P7: std 3,
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; CHECK-P7: lfd 1,
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; CHECK: mtvsrd 1, 3
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}
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