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aee5f0fc5d
- Relex hard coded registers and stack frame sizes - Some test cleanups - Change phi-dbg.ll to match on mir output after phi elimination instead of going through the whole codegen pipeline. This is in preparation for https://reviews.llvm.org/D52010 I'm committing all the test changes upfront that work before and after independently. llvm-svn: 345532
31 lines
897 B
YAML
31 lines
897 B
YAML
# RUN: llc -verify-machineinstrs -run-pass regallocfast -mtriple s390x-ibm-linux -o - %s | FileCheck %s
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--- |
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@g_167 = external global [5 x i64], align 8
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define void @main() local_unnamed_addr {
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ret void
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}
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...
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# Make sure the usage of different subregisters on the same virtual register
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# does not result in invalid kill flags.
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# PR33677
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---
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name: main
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alignment: 2
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tracksRegLiveness: true
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# CHECK: $r0l = COPY renamable $r1l
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# Although R0L partially redefines R0Q, it must not mark R0Q as kill
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# because R1D is still live through that instruction.
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# CHECK-NOT: implicit killed $r0q
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# CHECK-NEXT: {{\$r[0-9]+d}} = COPY renamable $r1d
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# CHECK-NEXT: LARL
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body: |
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bb.0:
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%0 : gr128bit = IMPLICIT_DEF
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%0.subreg_hl32 = COPY %0.subreg_l32
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%1 : gr64bit = COPY %0.subreg_l64
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%2 : addr64bit = LARL @g_167
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STC %1.subreg_l32, %2, 8, $noreg
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...
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