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llvm-mirror/test/MC/AArch64/armv8.4a-ras.s
Pablo Barrio db89df99c7 [AArch64] Enable RAS 1.1 system registers in all AArch64
Some use cases (e.g. kernel devs) have strict requirements to only enable
features available with -march=armv8-a, e.g. no armv8.1-a. Enabling RAS 1.1 in
all AArch64 means they can consider to support it.

Bear in mind that the first versions of the Armv8 architecture still do not
support RAS 1.1. This patch only lets devs write code with the user-friendly
register mnemonic instead of the ugly generic S<op0>_<op1>_<Cn>_<Cm>_<op2>.
They still need to place runtime checks to make sure that the CPU to run on
supports RAS 1.1.

Differential Revision: https://reviews.llvm.org/D90594
2020-11-10 12:13:33 +00:00

41 lines
1.3 KiB
ArmAsm

// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK
// RUN: FileCheck --check-prefix=CHECK-RO < %t %s
//------------------------------------------------------------------------------
// ARMV8.4-A RAS Extensions
//------------------------------------------------------------------------------
// Read/Write registers:
msr ERXPFGCTL_EL1, x0
mrs x0,ERXPFGCTL_EL1
//CHECK: msr ERXPFGCTL_EL1, x0 // encoding: [0xa0,0x54,0x18,0xd5]
//CHECK: mrs x0, ERXPFGCTL_EL1 // encoding: [0xa0,0x54,0x38,0xd5]
msr ERXPFGCDN_EL1, x0
mrs x0,ERXPFGCDN_EL1
//CHECK: msr ERXPFGCDN_EL1, x0 // encoding: [0xc0,0x54,0x18,0xd5]
//CHECK: mrs x0, ERXPFGCDN_EL1 // encoding: [0xc0,0x54,0x38,0xd5]
msr ERXMISC2_EL1, x0
mrs x0, ERXMISC2_EL1
//CHECK: msr ERXMISC2_EL1, x0 // encoding: [0x40,0x55,0x18,0xd5]
//CHECK: mrs x0, ERXMISC2_EL1 // encoding: [0x40,0x55,0x38,0xd5]
msr ERXMISC3_EL1, x0
mrs x0, ERXMISC3_EL1
//CHECK: msr ERXMISC3_EL1, x0 // encoding: [0x60,0x55,0x18,0xd5]
//CHECK: mrs x0, ERXMISC3_EL1 // encoding: [0x60,0x55,0x38,0xd5]
// Read-only registers:
mrs x0,ERXPFGF_EL1
msr ERXPFGF_EL1, x0
//CHECK: mrs x0, ERXPFGF_EL1 // encoding: [0x80,0x54,0x38,0xd5]
//CHECK-RO: error: expected writable system register or pstate