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b555d38aa1
This allows for a much more efficient encoding for small negative numbers by storing the sign bit first and negating the rest of the bits. This was already being used for OPC_CheckInteger. For every in tree target this affects, the table got smaller. R600GenDAGISel.inc saw the largest reduction of 7K. I did have to add a new opcode for StringIntegers used for register class ids and subregister indices since we don't have the integer value to encode. The enum name is emitted directly into the table. Previously assumed the enum would expand to a positive 7-bit number. We might be able to just shift that right by 1 and assume it is a positive 6 bit number, but that will need more investigation.
109 lines
3.5 KiB
TableGen
109 lines
3.5 KiB
TableGen
// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s -o %t
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// RUN: FileCheck --check-prefix=ADD %s < %t
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// RUN: FileCheck --check-prefix=ADDINT %s < %t
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// RUN: FileCheck --check-prefix=SUB %s < %t
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// RUN: FileCheck --check-prefix=MULINT %s < %t
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include "llvm/Target/Target.td"
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def TestInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestInstrInfo;
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}
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class TestEncoding : Instruction {
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field bits<32> Inst;
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}
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class TestReg<int index> : Register<"R"#index, []> {
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let HWEncoding{15...4} = 0;
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let HWEncoding{3...0} = !cast<bits<4>>(index);
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}
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foreach i = 0...15 in
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def "R"#i : TestReg<i>;
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def Reg : RegisterClass<"TestTarget", [i32], 32, (sequence "R%d", 0, 15)>;
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def IntOperand: Operand<i32>;
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def OptionalIntOperand: OperandWithDefaultOps<i32, (ops (i32 0))>;
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class RRI<string Mnemonic, bits<4> Opcode> : TestEncoding {
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dag OutOperandList = (outs Reg:$dest);
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dag InOperandList = (ins Reg:$src1, Reg:$src2, OptionalIntOperand:$imm);
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string AsmString = Mnemonic # " $dest1, $src1, $src2, #$imm";
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string AsmVariantName = "";
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field bits<4> dest;
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field bits<4> src1;
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field bits<4> src2;
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field bits<16> imm;
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let Inst{31...28} = Opcode;
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let Inst{27...24} = dest;
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let Inst{23...20} = src1;
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let Inst{19...16} = src2;
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let Inst{15...0} = imm;
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}
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def AddRRI : RRI<"add", 0b0001>;
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// I define one of these intrinsics with IntrNoMem and the other
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// without it, so that they'll match different top-level DAG opcodes
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// (INTRINSIC_WO_CHAIN and INTRINSIC_W_CHAIN), which makes the
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// FileCheck-herding easier, because every case I want to detect
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// should show up as a separate top-level switch element.
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def int_addplus1 : Intrinsic<
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[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_mul3 : Intrinsic<
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[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty]>;
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def AddPat : Pat<(add i32:$x, i32:$y),
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(AddRRI Reg:$x, Reg:$y)>;
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def Add1Pat : Pat<(int_addplus1 i32:$x, i32:$y),
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(AddRRI Reg:$x, Reg:$y, (i32 1))>;
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def SubRRI : RRI<"sub", 0b0010> {
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let Pattern = [(set Reg:$dest, (sub Reg:$src1, Reg:$src2))];
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}
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def MulRRI : RRI<"mul", 0b0011> {
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let Pattern = [(set Reg:$dest, (int_mul3 Reg:$src1, Reg:$src2, i32:$imm))];
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}
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def MulIRR : RRI<"mul2", 0b0100> {
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let InOperandList = (ins OptionalIntOperand:$imm, Reg:$src1, Reg:$src2);
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}
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def MulIRRPat : Pat<(mul i32:$x, i32:$y), (MulIRR Reg:$x, Reg:$y)>;
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// ADD: SwitchOpcode{{.*}}TARGET_VAL(ISD::ADD)
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// ADD-NEXT: OPC_RecordChild0
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// ADD-NEXT: OPC_RecordChild1
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// ADD-NEXT: OPC_EmitInteger, MVT::i32, 0
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// ADD-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::AddRRI)
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// ADDINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_WO_CHAIN)
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// ADDINT-NEXT: OPC_CheckChild0Integer
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// ADDINT-NEXT: OPC_RecordChild1
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// ADDINT-NEXT: OPC_RecordChild2
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// ADDINT-NEXT: OPC_EmitInteger, MVT::i32, 2
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// ADDINT-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::AddRRI)
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// SUB: SwitchOpcode{{.*}}TARGET_VAL(ISD::SUB)
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// SUB-NEXT: OPC_RecordChild0
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// SUB-NEXT: OPC_RecordChild1
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// SUB-NEXT: OPC_EmitInteger, MVT::i32, 0
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// SUB-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::SubRRI)
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// MULINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_W_CHAIN)
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// MULINT-NEXT: OPC_RecordNode
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// MULINT-NEXT: OPC_CheckChild1Integer
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// MULINT-NEXT: OPC_RecordChild2
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// MULINT-NEXT: OPC_RecordChild3
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// MULINT-NEXT: OPC_RecordChild4
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// MULINT-NEXT: OPC_EmitMergeInputChains
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// MULINT-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::MulRRI)
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// MUL: SwitchOpcode{{.*}}TARGET_VAL(ISD::MUL)
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// MUL-NEXT: OPC_EmitInteger, MVT::i32, 0
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// MUL-NEXT: OPC_RecordChild0
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// MUL-NEXT: OPC_RecordChild1
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// MUL-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::MulRRI)
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