Craig Topper 11c658c4e5 [DAGCombiner] Minor compile time improvement to (sext_in_reg (sign_extend_vector_inreg x)) optimization. ... Don't bother calling ComputeNumSignBits if N00Bits < ExtVTBits. No matter what answer we get back this will be true: (N00Bits - DAG.ComputeNumSignBits(N00, DemandedSrcElts)) < ExtVTBits) So we might as well save the computation. This makes the code more consistent with the similar (sext_in_reg (sext x)) handling above.		2021-03-21 11:16:41 -07:00
..
CMakeLists.txt
DAGCombiner.cpp	[DAGCombiner] Minor compile time improvement to (sext_in_reg (sign_extend_vector_inreg x)) optimization.	2021-03-21 11:16:41 -07:00
FastISel.cpp	[FastISel] Don't trivially kill extractvalues (PR49467)	2021-03-09 18:46:38 +01:00
FunctionLoweringInfo.cpp	[NFC] Wisely nest dyn_cast in FunctionLoweringInfo	2021-03-16 10:22:44 +01:00
InstrEmitter.cpp	[DebugInfo] Emit DBG_VALUE_LIST from ISel	2021-03-09 12:17:39 +00:00
InstrEmitter.h	[DebugInfo] Emit DBG_VALUE_LIST from ISel	2021-03-09 12:17:39 +00:00
LegalizeDAG.cpp	[IR] Introduce llvm.experimental.vector.splice intrinsic	2021-03-09 10:44:22 +00:00
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp	[RISCV][SelectionDAG] Introduce an ISD::SPLAT_VECTOR_PARTS node that can represent a splat of 2 i32 values into a nxvXi64 vector for riscv32.	2021-03-10 09:46:18 -08:00
LegalizeTypes.cpp	[SelectionDAG] Use range-based for loops (NFC)	2021-02-09 22:14:30 -08:00
LegalizeTypes.h	[RISCV][SelectionDAG] Introduce an ISD::SPLAT_VECTOR_PARTS node that can represent a splat of 2 i32 values into a nxvXi64 vector for riscv32.	2021-03-10 09:46:18 -08:00
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp	[NFC] Unify FIME with FIXME in comments	2021-03-10 14:00:51 +01:00
LegalizeVectorTypes.cpp	[CodeGen] Fix issues with scalable-vector INSERT/EXTRACT_SUBVECTORs	2021-03-15 17:04:21 +00:00
ResourcePriorityQueue.cpp
ScheduleDAGFast.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp	[DebugInfo] Emit DBG_VALUE_LIST from ISel	2021-03-09 12:17:39 +00:00
ScheduleDAGSDNodes.h
ScheduleDAGVLIW.cpp	[SelectionDAG] Use range-based for loops (NFC)	2021-02-09 22:14:30 -08:00
SDNodeDbgValue.h	[DebugInfo] Handle dbg.values with multiple variable location operands in ISel	2021-03-09 09:48:03 +00:00
SelectionDAG.cpp	[DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling	2021-03-19 16:02:31 +00:00
SelectionDAGAddressAnalysis.cpp
SelectionDAGBuilder.cpp	Reapply "[DebugInfo] Handle multiple variable location operands in IR"	2021-03-17 16:45:25 +00:00
SelectionDAGBuilder.h	[IR] Introduce llvm.experimental.vector.splice intrinsic	2021-03-09 10:44:22 +00:00
SelectionDAGDumper.cpp	[RISCV][SelectionDAG] Introduce an ISD::SPLAT_VECTOR_PARTS node that can represent a splat of 2 i32 values into a nxvXi64 vector for riscv32.	2021-03-10 09:46:18 -08:00
SelectionDAGISel.cpp	[DebugInfo] Emit DBG_VALUE_LIST from ISel	2021-03-09 12:17:39 +00:00
SelectionDAGPrinter.cpp
SelectionDAGTargetInfo.cpp
StatepointLowering.cpp	[Statepoint Lowering] Handle the case with several gc.result	2021-03-11 18:44:44 +07:00
StatepointLowering.h
TargetLowering.cpp	[IR] Introduce llvm.experimental.vector.splice intrinsic	2021-03-09 10:44:22 +00:00