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llvm-mirror/test/CodeGen
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Mirko Brkusanin 09694f5b10 [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores 
Fix local ds_read/write_b96/b128 so they can be selected if the alignment
allows. Otherwise, either pick appropriate ds_read2/write2 instructions or break
them down.

Differential Revision: https://reviews.llvm.org/D81638
2020-08-21 12:26:31 +02:00
..
AArch64
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
AMDGPU
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
2020-08-21 12:26:31 +02:00
ARC
[ARC] Fix CodeGen/ARC/brcc.ll
2020-08-15 19:33:35 -07:00
ARM
[ARM][MachineOutliner] Add default mode.
2020-08-20 09:25:33 +02:00
AVR
…
BPF
BPF: add a SimplifyCFG IR pass during generic Scalar/IPO optimization
2020-08-06 13:16:00 -07:00
Generic
[Tests] Be consistent w/definition of statepoint-example
2020-08-14 20:45:48 -07:00
Hexagon
Revert "[BPI] Improve static heuristics for integer comparisons"
2020-08-17 20:44:33 +02:00
Inputs
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Lanai
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Mips
Revert "[BPI] Improve static heuristics for integer comparisons"
2020-08-17 20:44:33 +02:00
MIR
[AMDGPU] Reorganize GCN subtarget features for unaligned access
2020-08-21 12:26:31 +02:00
MSP430
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NVPTX
[NVPTX] Fix typo in lit test
2020-08-17 16:02:11 -04:00
PowerPC
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
RISCV
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
SPARC
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SystemZ
Revert "[BPI] Improve static heuristics for integer comparisons"
2020-08-17 20:44:33 +02:00
Thumb
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Thumb2
[ARM] Regenerate mve-vabd.ll test. NFC
2020-08-20 12:24:27 +01:00
VE
[VE] Support f128
2020-08-17 17:26:52 +09:00
WebAssembly
[WebAssembly] Fix FastISel address calculation bug
2020-08-08 15:23:11 -07:00
WinCFGuard
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WinEH
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X86
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
XCore
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