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llvm-mirror/test/CodeGen
Ulrich Weigand 096deccae0 [SystemZ] Handle sub-128 vectors
The ABI allows sub-128 vectors to be passed and returned in registers,
with the vector occupying the upper part of a register.  We therefore
want to legalize those types by widening the vector rather than promoting
the elements.

The patch includes some simple tests for sub-128 vectors and also tests
that we can recognize various pack sequences, some of which use sub-128
vectors as temporary results.  One of these forms is based on the pack
sequences generated by llvmpipe when no intrinsics are used.

Signed unpacks are recognized as BUILD_VECTORs whose elements are
individually sign-extended.  Unsigned unpacks can have the equivalent
form with zero extension, but they also occur as shuffles in which some
elements are zero.

Based on a patch by Richard Sandiford.

llvm-svn: 236525
2015-05-05 19:29:21 +00:00
..
AArch64 [ShrinkWrap] Add (a simplified version) of shrink-wrapping. 2015-05-05 17:38:16 +00:00
ARM Revert "Fix IfConverter to handle regmask machine operands." 2015-05-05 18:49:05 +00:00
BPF [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
CPP [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
Generic [Hexagon] r236351 fix does not work on builder configurations yet. 2015-05-01 22:39:20 +00:00
Hexagon IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Inputs IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Mips [mips] Generate code for insert/extract operations when using the N64 ABI and MSA. 2015-05-05 10:32:24 +00:00
MSP430 [opaque pointer type] Add textual IR support for explicit type parameter to gep operator 2015-03-13 18:20:45 +00:00
NVPTX [NVPTX] Handle addrspacecast constant expressions in aggregate initializers 2015-04-28 17:18:30 +00:00
PowerPC This patch adds ABI support for v1i128 data type. 2015-05-05 16:10:44 +00:00
R600 R600/SI: Add VCC as an implict def of SI_KILL 2015-05-01 03:44:09 +00:00
SPARC [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
SystemZ [SystemZ] Handle sub-128 vectors 2015-05-05 19:29:21 +00:00
Thumb IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Thumb2 Thumb2: When applying branch optimizations, visit branches in reverse order. 2015-04-23 20:31:35 +00:00
WinEH Flip r236172 testcase RUN option ordering for BSD sed(1). NFC. 2015-04-30 00:07:34 +00:00
X86 Re-land "[WinEH] Add an EH registration and state insertion pass for 32-bit x86" 2015-05-05 17:44:16 +00:00
XCore IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00