Geoff Berry 097bf66bf4 [MachineOperand][Target] MachineOperand::isRenamable semantics changes ... Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931		2018-02-23 18:25:08 +00:00
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AsmParser	[RISCV] Implement c.lui immediate operand constraint	2018-02-22 15:02:28 +00:00
Disassembler	[RISCV] Implement c.lui immediate operand constraint	2018-02-22 15:02:28 +00:00
InstPrinter	[RISCV] Pass MCSubtargetInfo to print methods.	2018-01-12 02:27:00 +00:00
MCTargetDesc	[RISCV][NFC] Make logic in RISCVMCCodeEmitter::getImmOpValue more defensive	2018-02-22 13:24:25 +00:00
TargetInfo	Fix RISCV build after r318352	2017-11-16 18:39:31 +00:00
CMakeLists.txt	[RISCV] Add custom CC_RISCV calling convention and improved call support	2017-12-11 12:49:02 +00:00
LLVMBuild.txt	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCV.h	[RISCV] Codegen support for memory operations on global addresses	2017-11-08 13:24:21 +00:00
RISCV.td	[MachineOperand][Target] MachineOperand::isRenamable semantics changes	2018-02-23 18:25:08 +00:00
RISCVAsmPrinter.cpp	[RISCV] Add basic support for inline asm constraints	2018-01-10 20:05:09 +00:00
RISCVCallingConv.td	[RISCV] Add custom CC_RISCV calling convention and improved call support	2017-12-11 12:49:02 +00:00
RISCVFrameLowering.cpp	[RISCV] Implement frame pointer elimination	2018-01-18 11:34:02 +00:00
RISCVFrameLowering.h	[RISCV] Reserve an emergency spill slot for the register scavenger when necessary	2018-01-11 11:17:19 +00:00
RISCVInstrFormats.td	[RISCV] MC layer support for load/store instructions of the C (compressed) extension	2017-12-07 12:50:32 +00:00
RISCVInstrFormatsC.td	[RISCV] MC layer support for the remaining RVC instructions	2017-12-13 09:32:55 +00:00
RISCVInstrInfo.cpp	[RISCV] Implement support for the BranchRelaxation pass	2018-01-10 21:05:07 +00:00
RISCVInstrInfo.h	[RISCV] Implement support for the BranchRelaxation pass	2018-01-10 21:05:07 +00:00
RISCVInstrInfo.td	[RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools	2017-12-13 12:46:55 +00:00
RISCVInstrInfoA.td	[RISCV] MC layer support for the standard RV64A instruction set extension	2017-12-07 10:59:12 +00:00
RISCVInstrInfoC.td	[RISCV] Implement c.lui immediate operand constraint	2018-02-22 15:02:28 +00:00
RISCVInstrInfoD.td	[RISCV] Implement floating point assembler pseudo instructions	2017-12-13 11:37:19 +00:00
RISCVInstrInfoF.td	[RISCV] Implement floating point assembler pseudo instructions	2017-12-13 11:37:19 +00:00
RISCVInstrInfoM.td	[RISCV] Codegen support for the standard RV32M instruction set extension	2018-01-18 12:36:38 +00:00
RISCVISelDAGToDAG.cpp	[SelectionDAGISel] Add a debug print before call to Select. Adjust where blank lines are printed during isel process to make things more sensibly grouped.	2018-01-26 19:34:20 +00:00
RISCVISelLowering.cpp	[RISCV] Define getSetCCResultType for setting vector setCC type	2018-02-02 02:43:18 +00:00
RISCVISelLowering.h	[RISCV] Define getSetCCResultType for setting vector setCC type	2018-02-02 02:43:18 +00:00
RISCVMachineFunctionInfo.h	[RISCV] Support for varargs	2018-01-10 19:41:03 +00:00
RISCVMCInstLower.cpp	[RISCV] Implement support for the BranchRelaxation pass	2018-01-10 21:05:07 +00:00
RISCVRegisterInfo.cpp	[RISCV] Implement frame pointer elimination	2018-01-18 11:34:02 +00:00
RISCVRegisterInfo.h	[RISCV] Implement support for the BranchRelaxation pass	2018-01-10 21:05:07 +00:00
RISCVRegisterInfo.td	[RISCV] MC layer support for the remaining RVC instructions	2017-12-13 09:32:55 +00:00
RISCVSubtarget.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVSubtarget.h	[RISCV] MC layer support for load/store instructions of the C (compressed) extension	2017-12-07 12:50:32 +00:00
RISCVTargetMachine.cpp	[RISCV] Implement support for the BranchRelaxation pass	2018-01-10 21:05:07 +00:00
RISCVTargetMachine.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00