Thomas Lively 557b2fcc24 [WebAssembly] SIMD conversions ... Summary: Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to int conversions produce poison values if their arguments are out of the convertible range, so a future CL will have to add an LLVM intrinsic to make the saturating behavior of this conversion usable. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52372 llvm-svn: 343052		2018-09-26 00:34:36 +00:00
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AArch64	[AArch64] Attempt to parse more operands as expressions	2018-09-18 09:44:53 +00:00
AMDGPU	AMDGPU: Print all kernel descriptor directives (including the ones with default values)	2018-09-12 20:25:39 +00:00
ARM	[Arm][AsmParser] Restrict register list size for VSTM/VLDM	2018-09-24 15:13:48 +00:00
AsmParser	[debuginfo] generate debug info with asm+.file	2018-08-28 16:23:39 +00:00
AVR	[AVR] Redefine the 'SBR' instruction as an alias	2018-09-01 12:22:54 +00:00
BPF	bpf: New disassembler testcases for 32-bit subregister support	2018-02-23 23:49:35 +00:00
COFF	[codeview] Add .cv_string directive for testing purposes	2018-09-07 21:30:52 +00:00
Disassembler	[RISCV] Fix decoding of invalid instruction with C extension enabled.	2018-09-13 18:21:19 +00:00
ELF	[lib/MC] - Set SHF_EXCLUDE flag for .dwo sections.	2018-09-22 07:36:20 +00:00
Hexagon	Check for tied operands	2018-08-13 14:01:25 +00:00
Lanai
MachO	[MC/Dwarf] Unclamp DWARF linetables format on Darwin.	2018-09-13 13:13:50 +00:00
Mips	[mips] Fix MIPS N32 ABI triples support	2018-09-17 21:21:57 +00:00
PowerPC	[MC] Avoid inlining constant symbols with variants.	2018-09-17 20:34:26 +00:00
RISCV	[RISCV][MC] Improve parsing of jal/j operands	2018-09-20 08:10:35 +00:00
Sparc	[Sparc] allow tls_add/tls_call syntax in assembler parser	2018-09-03 10:38:12 +00:00
SystemZ
WebAssembly	[WebAssembly] SIMD conversions	2018-09-26 00:34:36 +00:00
X86	[X86][Assembler] Allow %eip as a register in 32-bit mode for .cfi directives.	2018-09-06 02:03:14 +00:00