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060bccc1f3
Summary: Instead of trying to replace SMRD instructions with a VGPR base pointer with an equivalent MUBUF instruction, we now copy the base pointer to SGPRs using v_readfirstlane. This is safe to do, because any load selected as an SMRD instruction has been proven to have a uniform base pointer, so each thread in the wave will have the same pointer value in VGPRs. This will fix some errors on VI from trying to replace SMRD instructions with addr64-enabled MUBUF instructions that don't exist. Reviewers: arsenm, cfang, nhaehnle Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D17305 llvm-svn: 261385
29 lines
1.0 KiB
LLVM
29 lines
1.0 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
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@ptr_load = addrspace(3) global i32 addrspace(2)* undef, align 8
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; Make sure when the load from %ptr2 is folded the chain isn't lost,
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; resulting in losing the store to gptr
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; FUNC-LABEL: {{^}}missing_store_reduced:
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; SI: ds_read_b64
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; SI: buffer_store_dword
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; SI: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
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; SI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
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; SI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}
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; SI: buffer_store_dword
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; SI: s_endpgm
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define void @missing_store_reduced(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
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%ptr0 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(3)* @ptr_load, align 8
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%ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 2
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store i32 99, i32 addrspace(1)* %gptr, align 4
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%tmp2 = load i32, i32 addrspace(2)* %ptr2, align 4
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store i32 %tmp2, i32 addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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