David Green 09c3fe91e2 [ARM] Adjust isLegalT1AddressImmediate for non-legal types ... Types such as float and i64's do not have legal loads in Thumb1, but will still be loaded with a LDR (or potentially multiple LDR's). As such we can treat the cost of addressing mode calculations the same as an i32 and get some optimisation benefits. Differential Revision: https://reviews.llvm.org/D62968 llvm-svn: 362874		2019-06-08 10:32:53 +00:00
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AArch64	[CostModel][X86][AArch64] Adjust cost of the scalarization part of min/max reduction.	2018-12-10 06:58:58 +00:00
AMDGPU	TTI: Improve default costs for addrspacecast	2019-06-03 18:41:34 +00:00
ARM	[ARM] Adjust isLegalT1AddressImmediate for non-legal types	2019-06-08 10:32:53 +00:00
PowerPC	Revert "[llvm] r359313 - [PowerPC] Update P9 vector costs for insert/extract element"	2019-05-01 05:01:03 +00:00
RISCV	[RISCV] Disable test/Analysis/CostModel/RISCV tests if RISCV backend not built	2019-06-06 10:12:28 +00:00
SystemZ	[CodeMetrics] Don't let extends of i1 be free.	2019-05-17 01:26:35 +00:00
X86	[CostModel][X86] Improve masked load/store AVX1/AVX2 costs	2019-06-02 20:37:02 +00:00
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