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7fff32705f
Much like ValueTypeByHwMode/RegInfoByHwMode, this patch allows targets to modify an instruction's encoding based on HwMode. When the EncodingInfos field is non-empty the Inst and Size fields of the Instruction are ignored and taken from EncodingInfos instead. As part of this promote getHwMode() from TargetSubtargetInfo to MCSubtargetInfo. This is NFC for all existing targets - new code is generated only if targets use EncodingByHwMode. llvm-svn: 372320
195 lines
5.7 KiB
C++
195 lines
5.7 KiB
C++
//===--- InfoByHwMode.h -----------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Classes that implement data parameterized by HW modes for instruction
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// selection. Currently it is ValueTypeByHwMode (parameterized ValueType),
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// and RegSizeInfoByHwMode (parameterized register/spill size and alignment
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// data).
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_UTILS_TABLEGEN_INFOBYHWMODE_H
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#define LLVM_UTILS_TABLEGEN_INFOBYHWMODE_H
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#include "CodeGenHwModes.h"
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#include "llvm/Support/MachineValueType.h"
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#include <map>
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#include <set>
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#include <string>
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#include <vector>
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namespace llvm {
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struct CodeGenHwModes;
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class Record;
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class raw_ostream;
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template <typename InfoT> struct InfoByHwMode;
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std::string getModeName(unsigned Mode);
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enum : unsigned {
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DefaultMode = CodeGenHwModes::DefaultMode,
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};
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template <typename InfoT>
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std::vector<unsigned> union_modes(const InfoByHwMode<InfoT> &A,
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const InfoByHwMode<InfoT> &B) {
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std::vector<unsigned> V;
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std::set<unsigned> U;
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for (const auto &P : A)
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U.insert(P.first);
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for (const auto &P : B)
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U.insert(P.first);
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// Make sure that the default mode is last on the list.
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bool HasDefault = false;
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for (unsigned M : U)
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if (M != DefaultMode)
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V.push_back(M);
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else
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HasDefault = true;
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if (HasDefault)
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V.push_back(DefaultMode);
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return V;
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}
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template <typename InfoT>
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struct InfoByHwMode {
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typedef std::map<unsigned,InfoT> MapType;
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typedef typename MapType::value_type PairType;
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typedef typename MapType::iterator iterator;
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typedef typename MapType::const_iterator const_iterator;
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InfoByHwMode() = default;
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InfoByHwMode(const MapType &M) : Map(M) {}
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LLVM_ATTRIBUTE_ALWAYS_INLINE
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iterator begin() { return Map.begin(); }
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LLVM_ATTRIBUTE_ALWAYS_INLINE
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iterator end() { return Map.end(); }
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LLVM_ATTRIBUTE_ALWAYS_INLINE
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const_iterator begin() const { return Map.begin(); }
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LLVM_ATTRIBUTE_ALWAYS_INLINE
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const_iterator end() const { return Map.end(); }
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LLVM_ATTRIBUTE_ALWAYS_INLINE
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bool empty() const { return Map.empty(); }
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LLVM_ATTRIBUTE_ALWAYS_INLINE
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bool hasMode(unsigned M) const { return Map.find(M) != Map.end(); }
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LLVM_ATTRIBUTE_ALWAYS_INLINE
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bool hasDefault() const { return hasMode(DefaultMode); }
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InfoT &get(unsigned Mode) {
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if (!hasMode(Mode)) {
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assert(hasMode(DefaultMode));
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Map.insert({Mode, Map.at(DefaultMode)});
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}
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return Map.at(Mode);
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}
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const InfoT &get(unsigned Mode) const {
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auto F = Map.find(Mode);
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if (Mode != DefaultMode && F == Map.end())
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F = Map.find(DefaultMode);
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assert(F != Map.end());
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return F->second;
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}
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LLVM_ATTRIBUTE_ALWAYS_INLINE
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bool isSimple() const {
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return Map.size() == 1 && Map.begin()->first == DefaultMode;
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}
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LLVM_ATTRIBUTE_ALWAYS_INLINE
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InfoT getSimple() const {
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assert(isSimple());
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return Map.begin()->second;
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}
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void makeSimple(unsigned Mode) {
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assert(hasMode(Mode) || hasDefault());
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InfoT I = get(Mode);
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Map.clear();
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Map.insert(std::make_pair(DefaultMode, I));
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}
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MapType Map;
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};
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struct ValueTypeByHwMode : public InfoByHwMode<MVT> {
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ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH);
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ValueTypeByHwMode(Record *R, MVT T);
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ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode,T}); }
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ValueTypeByHwMode() = default;
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bool operator== (const ValueTypeByHwMode &T) const;
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bool operator< (const ValueTypeByHwMode &T) const;
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bool isValid() const {
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return !Map.empty();
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}
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MVT getType(unsigned Mode) const { return get(Mode); }
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MVT &getOrCreateTypeForMode(unsigned Mode, MVT Type);
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static StringRef getMVTName(MVT T);
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void writeToStream(raw_ostream &OS) const;
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void dump() const;
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unsigned PtrAddrSpace = std::numeric_limits<unsigned>::max();
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bool isPointer() const {
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return PtrAddrSpace != std::numeric_limits<unsigned>::max();
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}
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};
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ValueTypeByHwMode getValueTypeByHwMode(Record *Rec,
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const CodeGenHwModes &CGH);
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struct RegSizeInfo {
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unsigned RegSize;
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unsigned SpillSize;
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unsigned SpillAlignment;
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RegSizeInfo(Record *R, const CodeGenHwModes &CGH);
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RegSizeInfo() = default;
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bool operator< (const RegSizeInfo &I) const;
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bool operator== (const RegSizeInfo &I) const {
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return std::tie(RegSize, SpillSize, SpillAlignment) ==
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std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
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}
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bool operator!= (const RegSizeInfo &I) const {
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return !(*this == I);
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}
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bool isSubClassOf(const RegSizeInfo &I) const;
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void writeToStream(raw_ostream &OS) const;
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};
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struct RegSizeInfoByHwMode : public InfoByHwMode<RegSizeInfo> {
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RegSizeInfoByHwMode(Record *R, const CodeGenHwModes &CGH);
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RegSizeInfoByHwMode() = default;
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bool operator< (const RegSizeInfoByHwMode &VI) const;
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bool operator== (const RegSizeInfoByHwMode &VI) const;
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bool operator!= (const RegSizeInfoByHwMode &VI) const {
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return !(*this == VI);
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}
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bool isSubClassOf(const RegSizeInfoByHwMode &I) const;
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bool hasStricterSpillThan(const RegSizeInfoByHwMode &I) const;
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void writeToStream(raw_ostream &OS) const;
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};
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raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T);
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raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T);
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raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T);
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struct EncodingInfoByHwMode : public InfoByHwMode<Record*> {
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EncodingInfoByHwMode(Record *R, const CodeGenHwModes &CGH);
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EncodingInfoByHwMode() = default;
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};
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} // namespace llvm
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#endif // LLVM_UTILS_TABLEGEN_INFOBYHWMODE_H
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