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647e2e70ab
This fixes znver1 so that it properly enables CMPXHG8B. We can probably remove explicit CMPXCHG8B from CPUs that also have CMPXCHG16B, but keeping this simple to allow cherry pick to 9.0. Fixes PR42935. llvm-svn: 368324
1268 lines
63 KiB
TableGen
1268 lines
63 KiB
TableGen
//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a target description file for the Intel i386 architecture, referred
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// to here as the "X86" architecture.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// X86 Subtarget state
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//
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def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
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"64-bit mode (x86_64)">;
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def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
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"32-bit mode (80386)">;
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def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
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"16-bit mode (i8086)">;
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//===----------------------------------------------------------------------===//
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// X86 Subtarget features
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//===----------------------------------------------------------------------===//
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def FeatureX87 : SubtargetFeature<"x87","HasX87", "true",
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"Enable X87 float instructions">;
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def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true",
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"Enable NOPL instruction">;
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def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
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"Enable conditional move instructions">;
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def FeatureCMPXCHG8B : SubtargetFeature<"cx8", "HasCmpxchg8b", "true",
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"Support CMPXCHG8B instructions">;
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def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
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"Support POPCNT instruction">;
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def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true",
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"Support fxsave/fxrestore instructions">;
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def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true",
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"Support xsave instructions">;
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def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
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"Support xsaveopt instructions">;
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def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
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"Support xsavec instructions">;
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def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true",
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"Support xsaves instructions">;
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def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
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"Enable SSE instructions">;
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def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
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"Enable SSE2 instructions",
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[FeatureSSE1]>;
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def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
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"Enable SSE3 instructions",
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[FeatureSSE2]>;
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def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
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"Enable SSSE3 instructions",
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[FeatureSSE3]>;
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def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
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"Enable SSE 4.1 instructions",
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[FeatureSSSE3]>;
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def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
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"Enable SSE 4.2 instructions",
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[FeatureSSE41]>;
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// The MMX subtarget feature is separate from the rest of the SSE features
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// because it's important (for odd compatibility reasons) to be able to
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// turn it off explicitly while allowing SSE+ to be on.
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def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
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"Enable MMX instructions">;
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
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"Enable 3DNow! instructions",
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[FeatureMMX]>;
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def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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"Enable 3DNow! Athlon instructions",
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[Feature3DNow]>;
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// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
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// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
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// without disabling 64-bit mode. Nothing should imply this feature bit. It
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// is used to enforce that only 64-bit capable CPUs are used in 64-bit mode.
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def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
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"Support 64-bit instructions">;
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def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
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"64-bit with cmpxchg16b",
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[FeatureCMPXCHG8B]>;
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def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
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"SHLD instruction is slow">;
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def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
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"PMULLD instruction is slow">;
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def FeatureSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
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"true",
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"PMADDWD is slower than PMULLD">;
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// FIXME: This should not apply to CPUs that do not have SSE.
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def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
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"IsUAMem16Slow", "true",
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"Slow unaligned 16-byte memory access">;
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def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
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"IsUAMem32Slow", "true",
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"Slow unaligned 32-byte memory access">;
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def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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"Support SSE 4a instructions",
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[FeatureSSE3]>;
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def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
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"Enable AVX instructions",
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[FeatureSSE42]>;
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def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
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"Enable AVX2 instructions",
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[FeatureAVX]>;
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def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
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"Enable three-operand fused multiple-add",
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[FeatureAVX]>;
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def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
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"Support 16-bit floating point conversion instructions",
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[FeatureAVX]>;
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def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
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"Enable AVX-512 instructions",
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[FeatureAVX2, FeatureFMA, FeatureF16C]>;
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def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
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"Enable AVX-512 Exponential and Reciprocal Instructions",
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[FeatureAVX512]>;
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def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
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"Enable AVX-512 Conflict Detection Instructions",
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[FeatureAVX512]>;
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def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
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"true", "Enable AVX-512 Population Count Instructions",
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[FeatureAVX512]>;
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def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
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"Enable AVX-512 PreFetch Instructions",
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[FeatureAVX512]>;
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def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1",
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"true",
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"Prefetch with Intent to Write and T1 Hint">;
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def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
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"Enable AVX-512 Doubleword and Quadword Instructions",
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[FeatureAVX512]>;
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def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
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"Enable AVX-512 Byte and Word Instructions",
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[FeatureAVX512]>;
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def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
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"Enable AVX-512 Vector Length eXtensions",
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[FeatureAVX512]>;
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def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
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"Enable AVX-512 Vector Byte Manipulation Instructions",
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[FeatureBWI]>;
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def FeatureVBMI2 : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true",
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"Enable AVX-512 further Vector Byte Manipulation Instructions",
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[FeatureBWI]>;
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def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
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"Enable AVX-512 Integer Fused Multiple-Add",
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[FeatureAVX512]>;
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def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true",
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"Enable protection keys">;
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def FeatureVNNI : SubtargetFeature<"avx512vnni", "HasVNNI", "true",
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"Enable AVX-512 Vector Neural Network Instructions",
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[FeatureAVX512]>;
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def FeatureBF16 : SubtargetFeature<"avx512bf16", "HasBF16", "true",
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"Support bfloat16 floating point",
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[FeatureBWI]>;
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def FeatureBITALG : SubtargetFeature<"avx512bitalg", "HasBITALG", "true",
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"Enable AVX-512 Bit Algorithms",
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[FeatureBWI]>;
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def FeatureVP2INTERSECT : SubtargetFeature<"avx512vp2intersect",
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"HasVP2INTERSECT", "true",
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"Enable AVX-512 vp2intersect",
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[FeatureAVX512]>;
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def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
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"Enable packed carry-less multiplication instructions",
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[FeatureSSE2]>;
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def FeatureGFNI : SubtargetFeature<"gfni", "HasGFNI", "true",
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"Enable Galois Field Arithmetic Instructions",
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[FeatureSSE2]>;
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def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true",
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"Enable vpclmulqdq instructions",
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[FeatureAVX, FeaturePCLMUL]>;
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def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
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"Enable four-operand fused multiple-add",
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[FeatureAVX, FeatureSSE4A]>;
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def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
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"Enable XOP instructions",
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[FeatureFMA4]>;
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def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
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"HasSSEUnalignedMem", "true",
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"Allow unaligned memory operands with SSE instructions">;
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def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
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"Enable AES instructions",
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[FeatureSSE2]>;
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def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true",
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"Promote selected AES instructions to AVX512/AVX registers",
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[FeatureAVX, FeatureAES]>;
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def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
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"Enable TBM instructions">;
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def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true",
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"Enable LWP instructions">;
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def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
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"Support MOVBE instruction">;
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def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
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"Support RDRAND instruction">;
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def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
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"Support FS/GS Base instructions">;
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def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
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"Support LZCNT instruction">;
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def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
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"Support BMI instructions">;
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def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
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"Support BMI2 instructions">;
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def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
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"Support RTM instructions">;
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def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
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"Support ADX instructions">;
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def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
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"Enable SHA instructions",
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[FeatureSSE2]>;
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def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true",
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"Support CET Shadow-Stack instructions">;
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def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
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"Support PRFCHW instructions">;
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def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
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"Support RDSEED instruction">;
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def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
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"Support LAHF and SAHF instructions">;
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def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
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"Enable MONITORX/MWAITX timer functionality">;
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def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true",
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"Enable Cache Line Zero">;
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def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
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"Enable Cache Demote">;
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def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
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"Support ptwrite instruction">;
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def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
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"Support MPX instructions">;
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def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
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"Use LEA for adjusting the stack pointer">;
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def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
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"HasSlowDivide32", "true",
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"Use 8-bit divide for positive values less than 256">;
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def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
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"HasSlowDivide64", "true",
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"Use 32-bit divide for positive values less than 2^32">;
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def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
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"PadShortFunctions", "true",
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"Pad short functions">;
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def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
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"Invalidate Process-Context Identifier">;
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def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
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"Enable Software Guard Extensions">;
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def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
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"Flush A Cache Line Optimized">;
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def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true",
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"Cache Line Write Back">;
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def FeatureWBNOINVD : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",
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"Write Back No Invalidate">;
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def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
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"Support RDPID instructions">;
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def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",
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"Wait and pause enhancements">;
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def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true",
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"Has ENQCMD instructions">;
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// On some processors, instructions that implicitly take two memory operands are
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// slow. In practice, this means that CALL, PUSH, and POP with memory operands
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// should be avoided in favor of a MOV + register CALL/PUSH/POP.
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def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
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"SlowTwoMemOps", "true",
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"Two memory operand instructions are slow">;
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def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
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"LEA instruction needs inputs at AG stage">;
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def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
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"LEA instruction with certain arguments is slow">;
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def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
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"LEA instruction with 3 ops or certain registers is slow">;
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def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
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"INC and DEC instructions are slower than ADD and SUB">;
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def FeatureSoftFloat
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: SubtargetFeature<"soft-float", "UseSoftFloat", "true",
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"Use software floating point features">;
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def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
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"HasPOPCNTFalseDeps", "true",
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"POPCNT has a false dependency on dest register">;
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def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
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"HasLZCNTFalseDeps", "true",
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"LZCNT/TZCNT have a false dependency on dest register">;
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def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
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"platform configuration instruction">;
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// On recent X86 (port bound) processors, its preferable to combine to a single shuffle
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// using a variable mask over multiple fixed shuffles.
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def FeatureFastVariableShuffle
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: SubtargetFeature<"fast-variable-shuffle",
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"HasFastVariableShuffle",
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"true", "Shuffles with variable masks are fast">;
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// On some X86 processors, there is no performance hazard to writing only the
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// lower parts of a YMM or ZMM register without clearing the upper part.
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def FeatureFastPartialYMMorZMMWrite
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: SubtargetFeature<"fast-partial-ymm-or-zmm-write",
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"HasFastPartialYMMorZMMWrite",
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"true", "Partial writes to YMM/ZMM registers are fast">;
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// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
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// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
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// vector FSQRT has higher throughput than the corresponding NR code.
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// The idea is that throughput bound code is likely to be vectorized, so for
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// vectorized code we should care about the throughput of SQRT operations.
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// But if the code is scalar that probably means that the code has some kind of
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// dependency and we should care more about reducing the latency.
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def FeatureFastScalarFSQRT
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: SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
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"true", "Scalar SQRT is fast (disable Newton-Raphson)">;
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def FeatureFastVectorFSQRT
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: SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
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"true", "Vector SQRT is fast (disable Newton-Raphson)">;
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// If lzcnt has equivalent latency/throughput to most simple integer ops, it can
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// be used to replace test/set sequences.
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def FeatureFastLZCNT
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: SubtargetFeature<
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"fast-lzcnt", "HasFastLZCNT", "true",
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"LZCNT instructions are as fast as most simple integer ops">;
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// If the target can efficiently decode NOPs upto 11-bytes in length.
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def FeatureFast11ByteNOP
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: SubtargetFeature<
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"fast-11bytenop", "HasFast11ByteNOP", "true",
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"Target can quickly decode up to 11 byte NOPs">;
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// If the target can efficiently decode NOPs upto 15-bytes in length.
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def FeatureFast15ByteNOP
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: SubtargetFeature<
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"fast-15bytenop", "HasFast15ByteNOP", "true",
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"Target can quickly decode up to 15 byte NOPs">;
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// Sandy Bridge and newer processors can use SHLD with the same source on both
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// inputs to implement rotate to avoid the partial flag update of the normal
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// rotate instructions.
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def FeatureFastSHLDRotate
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: SubtargetFeature<
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"fast-shld-rotate", "HasFastSHLDRotate", "true",
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"SHLD can be used as a faster rotate">;
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// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
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// "string operations"). See "REP String Enhancement" in the Intel Software
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// Development Manual. This feature essentially means that REP MOVSB will copy
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// using the largest available size instead of copying bytes one by one, making
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// it at least as fast as REPMOVS{W,D,Q}.
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def FeatureERMSB
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: SubtargetFeature<
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"ermsb", "HasERMSB", "true",
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"REP MOVS/STOS are fast">;
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// Bulldozer and newer processors can merge CMP/TEST (but not other
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// instructions) with conditional branches.
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def FeatureBranchFusion
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: SubtargetFeature<"branchfusion", "HasBranchFusion", "true",
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"CMP/TEST can be fused with conditional branches">;
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// Sandy Bridge and newer processors have many instructions that can be
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// fused with conditional branches and pass through the CPU as a single
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// operation.
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def FeatureMacroFusion
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: SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
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"Various instructions can be fused with conditional branches">;
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// Gather is available since Haswell (AVX2 set). So technically, we can
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// generate Gathers on all AVX2 processors. But the overhead on HSW is high.
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// Skylake Client processor has faster Gathers than HSW and performance is
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// similar to Skylake Server (AVX-512).
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def FeatureHasFastGather
|
|
: SubtargetFeature<"fast-gather", "HasFastGather", "true",
|
|
"Indicates if gather is reasonably fast">;
|
|
|
|
def FeaturePrefer256Bit
|
|
: SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true",
|
|
"Prefer 256-bit AVX instructions">;
|
|
|
|
// Lower indirect calls using a special construct called a `retpoline` to
|
|
// mitigate potential Spectre v2 attacks against them.
|
|
def FeatureRetpolineIndirectCalls
|
|
: SubtargetFeature<
|
|
"retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true",
|
|
"Remove speculation of indirect calls from the generated code">;
|
|
|
|
// Lower indirect branches and switches either using conditional branch trees
|
|
// or using a special construct called a `retpoline` to mitigate potential
|
|
// Spectre v2 attacks against them.
|
|
def FeatureRetpolineIndirectBranches
|
|
: SubtargetFeature<
|
|
"retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true",
|
|
"Remove speculation of indirect branches from the generated code">;
|
|
|
|
// Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and
|
|
// `retpoline-indirect-branches` above.
|
|
def FeatureRetpoline
|
|
: SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true",
|
|
"Remove speculation of indirect branches from the "
|
|
"generated code, either by avoiding them entirely or "
|
|
"lowering them with a speculation blocking construct",
|
|
[FeatureRetpolineIndirectCalls,
|
|
FeatureRetpolineIndirectBranches]>;
|
|
|
|
// Rely on external thunks for the emitted retpoline calls. This allows users
|
|
// to provide their own custom thunk definitions in highly specialized
|
|
// environments such as a kernel that does boot-time hot patching.
|
|
def FeatureRetpolineExternalThunk
|
|
: SubtargetFeature<
|
|
"retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
|
|
"When lowering an indirect call or branch using a `retpoline`, rely "
|
|
"on the specified user provided thunk rather than emitting one "
|
|
"ourselves. Only has effect when combined with some other retpoline "
|
|
"feature", [FeatureRetpolineIndirectCalls]>;
|
|
|
|
// Direct Move instructions.
|
|
def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
|
|
"Support movdiri instruction">;
|
|
def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
|
|
"Support movdir64b instruction">;
|
|
|
|
def FeatureFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true",
|
|
"Indicates that the BEXTR instruction is implemented as a single uop "
|
|
"with good throughput">;
|
|
|
|
// Combine vector math operations with shuffles into horizontal math
|
|
// instructions if a CPU implements horizontal operations (introduced with
|
|
// SSE3) with better latency/throughput than the alternative sequence.
|
|
def FeatureFastHorizontalOps
|
|
: SubtargetFeature<
|
|
"fast-hops", "HasFastHorizontalOps", "true",
|
|
"Prefer horizontal vector math instructions (haddp, phsub, etc.) over "
|
|
"normal vector instructions with shuffles", [FeatureSSE3]>;
|
|
|
|
def FeatureFastScalarShiftMasks
|
|
: SubtargetFeature<
|
|
"fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",
|
|
"Prefer a left/right scalar logical shift pair over a shift+and pair">;
|
|
|
|
def FeatureFastVectorShiftMasks
|
|
: SubtargetFeature<
|
|
"fast-vector-shift-masks", "HasFastVectorShiftMasks", "true",
|
|
"Prefer a left/right vector logical shift pair over a shift+and pair">;
|
|
|
|
// Merge branches using three-way conditional code.
|
|
def FeatureMergeToThreeWayBranch : SubtargetFeature<"merge-to-threeway-branch",
|
|
"ThreewayBranchProfitable", "true",
|
|
"Merge branches to a three-way "
|
|
"conditional branch">;
|
|
|
|
// Bonnell
|
|
def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">;
|
|
// Silvermont
|
|
def ProcIntelSLM : SubtargetFeature<"", "X86ProcFamily", "IntelSLM", "">;
|
|
// Goldmont
|
|
def ProcIntelGLM : SubtargetFeature<"", "X86ProcFamily", "IntelGLM", "">;
|
|
// Goldmont Plus
|
|
def ProcIntelGLP : SubtargetFeature<"", "X86ProcFamily", "IntelGLP", "">;
|
|
// Tremont
|
|
def ProcIntelTRM : SubtargetFeature<"", "X86ProcFamily", "IntelTRM", "">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "X86RegisterInfo.td"
|
|
include "X86RegisterBanks.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "X86Schedule.td"
|
|
include "X86InstrInfo.td"
|
|
include "X86SchedPredicates.td"
|
|
|
|
def X86InstrInfo : InstrInfo;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// X86 Scheduler Models
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "X86ScheduleAtom.td"
|
|
include "X86SchedSandyBridge.td"
|
|
include "X86SchedHaswell.td"
|
|
include "X86SchedBroadwell.td"
|
|
include "X86ScheduleSLM.td"
|
|
include "X86ScheduleZnver1.td"
|
|
include "X86ScheduleBdVer2.td"
|
|
include "X86ScheduleBtVer2.td"
|
|
include "X86SchedSkylakeClient.td"
|
|
include "X86SchedSkylakeServer.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// X86 Processor Feature Lists
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def ProcessorFeatures {
|
|
// Nehalem
|
|
list<SubtargetFeature> NHMInheritableFeatures = [FeatureX87,
|
|
FeatureCMPXCHG8B,
|
|
FeatureCMOV,
|
|
FeatureMMX,
|
|
FeatureSSE42,
|
|
FeatureFXSR,
|
|
FeatureNOPL,
|
|
Feature64Bit,
|
|
FeatureCMPXCHG16B,
|
|
FeaturePOPCNT,
|
|
FeatureLAHFSAHF,
|
|
FeatureMacroFusion];
|
|
list<SubtargetFeature> NHMSpecificFeatures = [];
|
|
list<SubtargetFeature> NHMFeatures =
|
|
!listconcat(NHMInheritableFeatures, NHMSpecificFeatures);
|
|
|
|
// Westmere
|
|
list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL];
|
|
list<SubtargetFeature> WSMSpecificFeatures = [];
|
|
list<SubtargetFeature> WSMInheritableFeatures =
|
|
!listconcat(NHMInheritableFeatures, WSMAdditionalFeatures);
|
|
list<SubtargetFeature> WSMFeatures =
|
|
!listconcat(WSMInheritableFeatures, WSMSpecificFeatures);
|
|
|
|
// Sandybridge
|
|
list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX,
|
|
FeatureSlowDivide64,
|
|
FeatureXSAVE,
|
|
FeatureXSAVEOPT,
|
|
FeatureSlow3OpsLEA,
|
|
FeatureFastScalarFSQRT,
|
|
FeatureFastSHLDRotate,
|
|
FeatureMergeToThreeWayBranch];
|
|
list<SubtargetFeature> SNBSpecificFeatures = [FeatureSlowUAMem32,
|
|
FeaturePOPCNTFalseDeps];
|
|
list<SubtargetFeature> SNBInheritableFeatures =
|
|
!listconcat(WSMInheritableFeatures, SNBAdditionalFeatures);
|
|
list<SubtargetFeature> SNBFeatures =
|
|
!listconcat(SNBInheritableFeatures, SNBSpecificFeatures);
|
|
|
|
// Ivybridge
|
|
list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND,
|
|
FeatureF16C,
|
|
FeatureFSGSBase];
|
|
list<SubtargetFeature> IVBSpecificFeatures = [FeatureSlowUAMem32,
|
|
FeaturePOPCNTFalseDeps];
|
|
list<SubtargetFeature> IVBInheritableFeatures =
|
|
!listconcat(SNBInheritableFeatures, IVBAdditionalFeatures);
|
|
list<SubtargetFeature> IVBFeatures =
|
|
!listconcat(IVBInheritableFeatures, IVBSpecificFeatures);
|
|
|
|
// Haswell
|
|
list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2,
|
|
FeatureBMI,
|
|
FeatureBMI2,
|
|
FeatureERMSB,
|
|
FeatureFMA,
|
|
FeatureINVPCID,
|
|
FeatureLZCNT,
|
|
FeatureMOVBE,
|
|
FeatureFastVariableShuffle];
|
|
list<SubtargetFeature> HSWSpecificFeatures = [FeaturePOPCNTFalseDeps,
|
|
FeatureLZCNTFalseDeps];
|
|
list<SubtargetFeature> HSWInheritableFeatures =
|
|
!listconcat(IVBInheritableFeatures, HSWAdditionalFeatures);
|
|
list<SubtargetFeature> HSWFeatures =
|
|
!listconcat(HSWInheritableFeatures, HSWSpecificFeatures);
|
|
|
|
// Broadwell
|
|
list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX,
|
|
FeatureRDSEED,
|
|
FeaturePRFCHW];
|
|
list<SubtargetFeature> BDWSpecificFeatures = [FeaturePOPCNTFalseDeps,
|
|
FeatureLZCNTFalseDeps];
|
|
list<SubtargetFeature> BDWInheritableFeatures =
|
|
!listconcat(HSWInheritableFeatures, BDWAdditionalFeatures);
|
|
list<SubtargetFeature> BDWFeatures =
|
|
!listconcat(BDWInheritableFeatures, BDWSpecificFeatures);
|
|
|
|
// Skylake
|
|
list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES,
|
|
FeatureMPX,
|
|
FeatureXSAVEC,
|
|
FeatureXSAVES,
|
|
FeatureCLFLUSHOPT,
|
|
FeatureFastVectorFSQRT];
|
|
list<SubtargetFeature> SKLSpecificFeatures = [FeatureHasFastGather,
|
|
FeaturePOPCNTFalseDeps,
|
|
FeatureSGX];
|
|
list<SubtargetFeature> SKLInheritableFeatures =
|
|
!listconcat(BDWInheritableFeatures, SKLAdditionalFeatures);
|
|
list<SubtargetFeature> SKLFeatures =
|
|
!listconcat(SKLInheritableFeatures, SKLSpecificFeatures);
|
|
|
|
// Skylake-AVX512
|
|
list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAVX512,
|
|
FeatureCDI,
|
|
FeatureDQI,
|
|
FeatureBWI,
|
|
FeatureVLX,
|
|
FeaturePKU,
|
|
FeatureCLWB];
|
|
list<SubtargetFeature> SKXSpecificFeatures = [FeatureHasFastGather,
|
|
FeaturePOPCNTFalseDeps];
|
|
list<SubtargetFeature> SKXInheritableFeatures =
|
|
!listconcat(SKLInheritableFeatures, SKXAdditionalFeatures);
|
|
list<SubtargetFeature> SKXFeatures =
|
|
!listconcat(SKXInheritableFeatures, SKXSpecificFeatures);
|
|
|
|
// Cascadelake
|
|
list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI];
|
|
list<SubtargetFeature> CLXSpecificFeatures = [FeatureHasFastGather,
|
|
FeaturePOPCNTFalseDeps];
|
|
list<SubtargetFeature> CLXInheritableFeatures =
|
|
!listconcat(SKXInheritableFeatures, CLXAdditionalFeatures);
|
|
list<SubtargetFeature> CLXFeatures =
|
|
!listconcat(CLXInheritableFeatures, CLXSpecificFeatures);
|
|
|
|
// Cooperlake
|
|
list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16];
|
|
list<SubtargetFeature> CPXSpecificFeatures = [FeatureHasFastGather,
|
|
FeaturePOPCNTFalseDeps];
|
|
list<SubtargetFeature> CPXInheritableFeatures =
|
|
!listconcat(CLXInheritableFeatures, CPXAdditionalFeatures);
|
|
list<SubtargetFeature> CPXFeatures =
|
|
!listconcat(CPXInheritableFeatures, CPXSpecificFeatures);
|
|
|
|
// Cannonlake
|
|
list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512,
|
|
FeatureCDI,
|
|
FeatureDQI,
|
|
FeatureBWI,
|
|
FeatureVLX,
|
|
FeaturePKU,
|
|
FeatureVBMI,
|
|
FeatureIFMA,
|
|
FeatureSHA,
|
|
FeatureSGX];
|
|
list<SubtargetFeature> CNLSpecificFeatures = [FeatureHasFastGather];
|
|
list<SubtargetFeature> CNLInheritableFeatures =
|
|
!listconcat(SKLInheritableFeatures, CNLAdditionalFeatures);
|
|
list<SubtargetFeature> CNLFeatures =
|
|
!listconcat(CNLInheritableFeatures, CNLSpecificFeatures);
|
|
|
|
// Icelake
|
|
list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG,
|
|
FeatureVAES,
|
|
FeatureVBMI2,
|
|
FeatureVNNI,
|
|
FeatureVPCLMULQDQ,
|
|
FeatureVPOPCNTDQ,
|
|
FeatureGFNI,
|
|
FeatureCLWB,
|
|
FeatureRDPID];
|
|
list<SubtargetFeature> ICLSpecificFeatures = [FeatureHasFastGather];
|
|
list<SubtargetFeature> ICLInheritableFeatures =
|
|
!listconcat(CNLInheritableFeatures, ICLAdditionalFeatures);
|
|
list<SubtargetFeature> ICLFeatures =
|
|
!listconcat(ICLInheritableFeatures, ICLSpecificFeatures);
|
|
|
|
// Icelake Server
|
|
list<SubtargetFeature> ICXSpecificFeatures = [FeaturePCONFIG,
|
|
FeatureWBNOINVD,
|
|
FeatureHasFastGather];
|
|
list<SubtargetFeature> ICXFeatures =
|
|
!listconcat(ICLInheritableFeatures, ICXSpecificFeatures);
|
|
|
|
// Atom
|
|
list<SubtargetFeature> AtomInheritableFeatures = [FeatureX87,
|
|
FeatureCMPXCHG8B,
|
|
FeatureCMOV,
|
|
FeatureMMX,
|
|
FeatureSSSE3,
|
|
FeatureFXSR,
|
|
FeatureNOPL,
|
|
Feature64Bit,
|
|
FeatureCMPXCHG16B,
|
|
FeatureMOVBE,
|
|
FeatureSlowTwoMemOps,
|
|
FeatureLAHFSAHF];
|
|
list<SubtargetFeature> AtomSpecificFeatures = [ProcIntelAtom,
|
|
FeatureSlowUAMem16,
|
|
FeatureLEAForSP,
|
|
FeatureSlowDivide32,
|
|
FeatureSlowDivide64,
|
|
FeatureLEAUsesAG,
|
|
FeaturePadShortFunctions];
|
|
list<SubtargetFeature> AtomFeatures =
|
|
!listconcat(AtomInheritableFeatures, AtomSpecificFeatures);
|
|
|
|
// Silvermont
|
|
list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,
|
|
FeaturePOPCNT,
|
|
FeaturePCLMUL,
|
|
FeaturePRFCHW,
|
|
FeatureSlowLEA,
|
|
FeatureSlowIncDec,
|
|
FeatureRDRAND];
|
|
list<SubtargetFeature> SLMSpecificFeatures = [ProcIntelSLM,
|
|
FeatureSlowDivide64,
|
|
FeatureSlowPMULLD,
|
|
FeaturePOPCNTFalseDeps];
|
|
list<SubtargetFeature> SLMInheritableFeatures =
|
|
!listconcat(AtomInheritableFeatures, SLMAdditionalFeatures);
|
|
list<SubtargetFeature> SLMFeatures =
|
|
!listconcat(SLMInheritableFeatures, SLMSpecificFeatures);
|
|
|
|
// Goldmont
|
|
list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES,
|
|
FeatureMPX,
|
|
FeatureSHA,
|
|
FeatureRDSEED,
|
|
FeatureXSAVE,
|
|
FeatureXSAVEOPT,
|
|
FeatureXSAVEC,
|
|
FeatureXSAVES,
|
|
FeatureCLFLUSHOPT,
|
|
FeatureFSGSBase];
|
|
list<SubtargetFeature> GLMSpecificFeatures = [ProcIntelGLM,
|
|
FeaturePOPCNTFalseDeps];
|
|
list<SubtargetFeature> GLMInheritableFeatures =
|
|
!listconcat(SLMInheritableFeatures, GLMAdditionalFeatures);
|
|
list<SubtargetFeature> GLMFeatures =
|
|
!listconcat(GLMInheritableFeatures, GLMSpecificFeatures);
|
|
|
|
// Goldmont Plus
|
|
list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE,
|
|
FeatureRDPID,
|
|
FeatureSGX];
|
|
list<SubtargetFeature> GLPSpecificFeatures = [ProcIntelGLP];
|
|
list<SubtargetFeature> GLPInheritableFeatures =
|
|
!listconcat(GLMInheritableFeatures, GLPAdditionalFeatures);
|
|
list<SubtargetFeature> GLPFeatures =
|
|
!listconcat(GLPInheritableFeatures, GLPSpecificFeatures);
|
|
|
|
// Tremont
|
|
list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLDEMOTE,
|
|
FeatureGFNI,
|
|
FeatureMOVDIRI,
|
|
FeatureMOVDIR64B,
|
|
FeatureWAITPKG];
|
|
list<SubtargetFeature> TRMSpecificFeatures = [ProcIntelTRM];
|
|
list<SubtargetFeature> TRMFeatures =
|
|
!listconcat(GLPInheritableFeatures, TRMAdditionalFeatures,
|
|
TRMSpecificFeatures);
|
|
|
|
// Knights Landing
|
|
list<SubtargetFeature> KNLFeatures = [FeatureX87,
|
|
FeatureCMPXCHG8B,
|
|
FeatureCMOV,
|
|
FeatureMMX,
|
|
FeatureFXSR,
|
|
FeatureNOPL,
|
|
Feature64Bit,
|
|
FeatureCMPXCHG16B,
|
|
FeaturePOPCNT,
|
|
FeatureSlowDivide64,
|
|
FeaturePCLMUL,
|
|
FeatureXSAVE,
|
|
FeatureXSAVEOPT,
|
|
FeatureLAHFSAHF,
|
|
FeatureSlow3OpsLEA,
|
|
FeatureSlowIncDec,
|
|
FeatureAES,
|
|
FeatureRDRAND,
|
|
FeatureF16C,
|
|
FeatureFSGSBase,
|
|
FeatureAVX512,
|
|
FeatureERI,
|
|
FeatureCDI,
|
|
FeaturePFI,
|
|
FeaturePREFETCHWT1,
|
|
FeatureADX,
|
|
FeatureRDSEED,
|
|
FeatureMOVBE,
|
|
FeatureLZCNT,
|
|
FeatureBMI,
|
|
FeatureBMI2,
|
|
FeatureFMA,
|
|
FeaturePRFCHW,
|
|
FeatureSlowTwoMemOps,
|
|
FeatureFastPartialYMMorZMMWrite,
|
|
FeatureHasFastGather,
|
|
FeatureSlowPMADDWD];
|
|
// TODO Add AVX5124FMAPS/AVX5124VNNIW features
|
|
list<SubtargetFeature> KNMFeatures =
|
|
!listconcat(KNLFeatures, [FeatureVPOPCNTDQ]);
|
|
|
|
// Barcelona
|
|
list<SubtargetFeature> BarcelonaInheritableFeatures = [FeatureX87,
|
|
FeatureCMPXCHG8B,
|
|
FeatureSSE4A,
|
|
Feature3DNowA,
|
|
FeatureFXSR,
|
|
FeatureNOPL,
|
|
FeatureCMPXCHG16B,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureSlowSHLD,
|
|
FeatureLAHFSAHF,
|
|
FeatureCMOV,
|
|
Feature64Bit,
|
|
FeatureFastScalarShiftMasks];
|
|
list<SubtargetFeature> BarcelonaFeatures = BarcelonaInheritableFeatures;
|
|
|
|
// Bobcat
|
|
list<SubtargetFeature> BtVer1InheritableFeatures = [FeatureX87,
|
|
FeatureCMPXCHG8B,
|
|
FeatureCMOV,
|
|
FeatureMMX,
|
|
FeatureSSSE3,
|
|
FeatureSSE4A,
|
|
FeatureFXSR,
|
|
FeatureNOPL,
|
|
Feature64Bit,
|
|
FeatureCMPXCHG16B,
|
|
FeaturePRFCHW,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureSlowSHLD,
|
|
FeatureLAHFSAHF,
|
|
FeatureFast15ByteNOP,
|
|
FeatureFastScalarShiftMasks,
|
|
FeatureFastVectorShiftMasks];
|
|
list<SubtargetFeature> BtVer1Features = BtVer1InheritableFeatures;
|
|
|
|
// Jaguar
|
|
list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX,
|
|
FeatureAES,
|
|
FeaturePCLMUL,
|
|
FeatureBMI,
|
|
FeatureF16C,
|
|
FeatureMOVBE,
|
|
FeatureXSAVE,
|
|
FeatureXSAVEOPT];
|
|
list<SubtargetFeature> BtVer2SpecificFeatures = [FeatureFastLZCNT,
|
|
FeatureFastBEXTR,
|
|
FeatureFastPartialYMMorZMMWrite,
|
|
FeatureFastHorizontalOps];
|
|
list<SubtargetFeature> BtVer2InheritableFeatures =
|
|
!listconcat(BtVer1InheritableFeatures, BtVer2AdditionalFeatures);
|
|
list<SubtargetFeature> BtVer2Features =
|
|
!listconcat(BtVer2InheritableFeatures, BtVer2SpecificFeatures);
|
|
|
|
// Bulldozer
|
|
list<SubtargetFeature> BdVer1InheritableFeatures = [FeatureX87,
|
|
FeatureCMPXCHG8B,
|
|
FeatureCMOV,
|
|
FeatureXOP,
|
|
Feature64Bit,
|
|
FeatureCMPXCHG16B,
|
|
FeatureAES,
|
|
FeaturePRFCHW,
|
|
FeaturePCLMUL,
|
|
FeatureMMX,
|
|
FeatureFXSR,
|
|
FeatureNOPL,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureXSAVE,
|
|
FeatureLWP,
|
|
FeatureSlowSHLD,
|
|
FeatureLAHFSAHF,
|
|
FeatureFast11ByteNOP,
|
|
FeatureFastScalarShiftMasks,
|
|
FeatureBranchFusion];
|
|
list<SubtargetFeature> BdVer1Features = BdVer1InheritableFeatures;
|
|
|
|
// PileDriver
|
|
list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C,
|
|
FeatureBMI,
|
|
FeatureTBM,
|
|
FeatureFMA,
|
|
FeatureFastBEXTR];
|
|
list<SubtargetFeature> BdVer2InheritableFeatures =
|
|
!listconcat(BdVer1InheritableFeatures, BdVer2AdditionalFeatures);
|
|
list<SubtargetFeature> BdVer2Features = BdVer2InheritableFeatures;
|
|
|
|
// Steamroller
|
|
list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT,
|
|
FeatureFSGSBase];
|
|
list<SubtargetFeature> BdVer3InheritableFeatures =
|
|
!listconcat(BdVer2InheritableFeatures, BdVer3AdditionalFeatures);
|
|
list<SubtargetFeature> BdVer3Features = BdVer3InheritableFeatures;
|
|
|
|
// Excavator
|
|
list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2,
|
|
FeatureBMI2,
|
|
FeatureMWAITX];
|
|
list<SubtargetFeature> BdVer4InheritableFeatures =
|
|
!listconcat(BdVer3InheritableFeatures, BdVer4AdditionalFeatures);
|
|
list<SubtargetFeature> BdVer4Features = BdVer4InheritableFeatures;
|
|
|
|
|
|
// AMD Zen Processors common ISAs
|
|
list<SubtargetFeature> ZNFeatures = [FeatureADX,
|
|
FeatureAES,
|
|
FeatureAVX2,
|
|
FeatureBMI,
|
|
FeatureBMI2,
|
|
FeatureCLFLUSHOPT,
|
|
FeatureCLZERO,
|
|
FeatureCMOV,
|
|
Feature64Bit,
|
|
FeatureCMPXCHG16B,
|
|
FeatureF16C,
|
|
FeatureFMA,
|
|
FeatureFSGSBase,
|
|
FeatureFXSR,
|
|
FeatureNOPL,
|
|
FeatureFastLZCNT,
|
|
FeatureLAHFSAHF,
|
|
FeatureLZCNT,
|
|
FeatureFastBEXTR,
|
|
FeatureFast15ByteNOP,
|
|
FeatureBranchFusion,
|
|
FeatureFastScalarShiftMasks,
|
|
FeatureMMX,
|
|
FeatureMOVBE,
|
|
FeatureMWAITX,
|
|
FeaturePCLMUL,
|
|
FeaturePOPCNT,
|
|
FeaturePRFCHW,
|
|
FeatureRDRAND,
|
|
FeatureRDSEED,
|
|
FeatureSHA,
|
|
FeatureSSE4A,
|
|
FeatureSlowSHLD,
|
|
FeatureX87,
|
|
FeatureXSAVE,
|
|
FeatureXSAVEC,
|
|
FeatureXSAVEOPT,
|
|
FeatureXSAVES];
|
|
list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,
|
|
FeatureRDPID,
|
|
FeatureWBNOINVD];
|
|
list<SubtargetFeature> ZN2Features =
|
|
!listconcat(ZNFeatures, ZN2AdditionalFeatures);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// X86 processors supported.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class Proc<string Name, list<SubtargetFeature> Features>
|
|
: ProcessorModel<Name, GenericModel, Features>;
|
|
|
|
// NOTE: CMPXCHG8B is here for legacy compatbility so that it is only disabled
|
|
// if i386/i486 is specifically requested.
|
|
def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16,
|
|
FeatureCMPXCHG8B]>;
|
|
def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>;
|
|
def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>;
|
|
def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16,
|
|
FeatureCMPXCHG8B]>;
|
|
def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16,
|
|
FeatureCMPXCHG8B]>;
|
|
def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16,
|
|
FeatureCMPXCHG8B, FeatureMMX]>;
|
|
|
|
def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
FeatureCMOV]>;
|
|
def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
FeatureCMOV, FeatureNOPL]>;
|
|
|
|
def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
FeatureMMX, FeatureCMOV, FeatureFXSR,
|
|
FeatureNOPL]>;
|
|
|
|
foreach P = ["pentium3", "pentium3m"] in {
|
|
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,FeatureMMX,
|
|
FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
|
|
}
|
|
|
|
// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
|
|
// The intent is to enable it for pentium4 which is the current default
|
|
// processor in a vanilla 32-bit clang compilation when no specific
|
|
// architecture is specified. This generally gives a nice performance
|
|
// increase on silvermont, with largely neutral behavior on other
|
|
// contemporary large core processors.
|
|
// pentium-m, pentium4m, prescott and nocona are included as a preventative
|
|
// measure to avoid performance surprises, in case clang's default cpu
|
|
// changes slightly.
|
|
|
|
def : ProcessorModel<"pentium-m", GenericPostRAModel,
|
|
[FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
|
|
FeatureCMOV]>;
|
|
|
|
foreach P = ["pentium4", "pentium4m"] in {
|
|
def : ProcessorModel<P, GenericPostRAModel,
|
|
[FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
|
|
FeatureCMOV]>;
|
|
}
|
|
|
|
// Intel Quark.
|
|
def : Proc<"lakemont", []>;
|
|
|
|
// Intel Core Duo.
|
|
def : ProcessorModel<"yonah", SandyBridgeModel,
|
|
[FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL,
|
|
FeatureCMOV]>;
|
|
|
|
// NetBurst.
|
|
def : ProcessorModel<"prescott", GenericPostRAModel,
|
|
[FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL,
|
|
FeatureCMOV]>;
|
|
def : ProcessorModel<"nocona", GenericPostRAModel, [
|
|
FeatureX87,
|
|
FeatureSlowUAMem16,
|
|
FeatureCMPXCHG8B,
|
|
FeatureCMOV,
|
|
FeatureMMX,
|
|
FeatureSSE3,
|
|
FeatureFXSR,
|
|
FeatureNOPL,
|
|
Feature64Bit,
|
|
FeatureCMPXCHG16B
|
|
]>;
|
|
|
|
// Intel Core 2 Solo/Duo.
|
|
def : ProcessorModel<"core2", SandyBridgeModel, [
|
|
FeatureX87,
|
|
FeatureSlowUAMem16,
|
|
FeatureCMPXCHG8B,
|
|
FeatureCMOV,
|
|
FeatureMMX,
|
|
FeatureSSSE3,
|
|
FeatureFXSR,
|
|
FeatureNOPL,
|
|
Feature64Bit,
|
|
FeatureCMPXCHG16B,
|
|
FeatureLAHFSAHF,
|
|
FeatureMacroFusion
|
|
]>;
|
|
def : ProcessorModel<"penryn", SandyBridgeModel, [
|
|
FeatureX87,
|
|
FeatureSlowUAMem16,
|
|
FeatureCMPXCHG8B,
|
|
FeatureCMOV,
|
|
FeatureMMX,
|
|
FeatureSSE41,
|
|
FeatureFXSR,
|
|
FeatureNOPL,
|
|
Feature64Bit,
|
|
FeatureCMPXCHG16B,
|
|
FeatureLAHFSAHF,
|
|
FeatureMacroFusion
|
|
]>;
|
|
|
|
// Atom CPUs.
|
|
foreach P = ["bonnell", "atom"] in {
|
|
def : ProcessorModel<P, AtomModel, ProcessorFeatures.AtomFeatures>;
|
|
}
|
|
|
|
foreach P = ["silvermont", "slm"] in {
|
|
def : ProcessorModel<P, SLMModel, ProcessorFeatures.SLMFeatures>;
|
|
}
|
|
|
|
def : ProcessorModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures>;
|
|
def : ProcessorModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures>;
|
|
def : ProcessorModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures>;
|
|
|
|
// "Arrandale" along with corei3 and corei5
|
|
foreach P = ["nehalem", "corei7"] in {
|
|
def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures>;
|
|
}
|
|
|
|
// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
|
|
def : ProcessorModel<"westmere", SandyBridgeModel,
|
|
ProcessorFeatures.WSMFeatures>;
|
|
|
|
foreach P = ["sandybridge", "corei7-avx"] in {
|
|
def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures>;
|
|
}
|
|
|
|
foreach P = ["ivybridge", "core-avx-i"] in {
|
|
def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures>;
|
|
}
|
|
|
|
foreach P = ["haswell", "core-avx2"] in {
|
|
def : ProcessorModel<P, HaswellModel, ProcessorFeatures.HSWFeatures>;
|
|
}
|
|
|
|
def : ProcessorModel<"broadwell", BroadwellModel,
|
|
ProcessorFeatures.BDWFeatures>;
|
|
|
|
def : ProcessorModel<"skylake", SkylakeClientModel,
|
|
ProcessorFeatures.SKLFeatures>;
|
|
|
|
// FIXME: define KNL scheduler model
|
|
def : ProcessorModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures>;
|
|
def : ProcessorModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures>;
|
|
|
|
foreach P = ["skylake-avx512", "skx"] in {
|
|
def : ProcessorModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures>;
|
|
}
|
|
|
|
def : ProcessorModel<"cascadelake", SkylakeServerModel,
|
|
ProcessorFeatures.CLXFeatures>;
|
|
def : ProcessorModel<"cooperlake", SkylakeServerModel,
|
|
ProcessorFeatures.CPXFeatures>;
|
|
def : ProcessorModel<"cannonlake", SkylakeServerModel,
|
|
ProcessorFeatures.CNLFeatures>;
|
|
def : ProcessorModel<"icelake-client", SkylakeServerModel,
|
|
ProcessorFeatures.ICLFeatures>;
|
|
def : ProcessorModel<"icelake-server", SkylakeServerModel,
|
|
ProcessorFeatures.ICXFeatures>;
|
|
|
|
// AMD CPUs.
|
|
|
|
def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
FeatureMMX]>;
|
|
def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
Feature3DNow]>;
|
|
def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
Feature3DNow]>;
|
|
|
|
foreach P = ["athlon", "athlon-tbird"] in {
|
|
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV,
|
|
Feature3DNowA, FeatureNOPL, FeatureSlowSHLD]>;
|
|
}
|
|
|
|
foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
|
|
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV,
|
|
FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL,
|
|
FeatureSlowSHLD]>;
|
|
}
|
|
|
|
foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
|
|
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
FeatureSSE2, Feature3DNowA, FeatureFXSR, FeatureNOPL,
|
|
Feature64Bit, FeatureSlowSHLD, FeatureCMOV,
|
|
FeatureFastScalarShiftMasks]>;
|
|
}
|
|
|
|
foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
|
|
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureSSE3,
|
|
Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B,
|
|
FeatureSlowSHLD, FeatureCMOV, Feature64Bit,
|
|
FeatureFastScalarShiftMasks]>;
|
|
}
|
|
|
|
foreach P = ["amdfam10", "barcelona"] in {
|
|
def : Proc<P, ProcessorFeatures.BarcelonaFeatures>;
|
|
}
|
|
|
|
// Bobcat
|
|
def : Proc<"btver1", ProcessorFeatures.BtVer1Features>;
|
|
// Jaguar
|
|
def : ProcessorModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features>;
|
|
|
|
// Bulldozer
|
|
def : ProcessorModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features>;
|
|
// Piledriver
|
|
def : ProcessorModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features>;
|
|
// Steamroller
|
|
def : Proc<"bdver3", ProcessorFeatures.BdVer3Features>;
|
|
// Excavator
|
|
def : Proc<"bdver4", ProcessorFeatures.BdVer4Features>;
|
|
|
|
def : ProcessorModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures>;
|
|
def : ProcessorModel<"znver2", Znver1Model, ProcessorFeatures.ZN2Features>;
|
|
|
|
def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
Feature3DNowA]>;
|
|
|
|
def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
|
|
def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
|
|
def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
|
|
def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
|
|
FeatureMMX, FeatureSSE1, FeatureFXSR,
|
|
FeatureCMOV]>;
|
|
|
|
// We also provide a generic 64-bit specific x86 processor model which tries to
|
|
// be good for modern chips without enabling instruction set encodings past the
|
|
// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
|
|
// modern 64-bit x86 chip, and enables features that are generally beneficial.
|
|
//
|
|
// We currently use the Sandy Bridge model as the default scheduling model as
|
|
// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
|
|
// covers a huge swath of x86 processors. If there are specific scheduling
|
|
// knobs which need to be tuned differently for AMD chips, we might consider
|
|
// forming a common base for them.
|
|
def : ProcessorModel<"x86-64", SandyBridgeModel, [
|
|
FeatureX87,
|
|
FeatureCMPXCHG8B,
|
|
FeatureCMOV,
|
|
FeatureMMX,
|
|
FeatureSSE2,
|
|
FeatureFXSR,
|
|
FeatureNOPL,
|
|
Feature64Bit,
|
|
FeatureSlow3OpsLEA,
|
|
FeatureSlowIncDec,
|
|
FeatureMacroFusion
|
|
]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Calling Conventions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "X86CallingConv.td"
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly Parser
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def ATTAsmParserVariant : AsmParserVariant {
|
|
int Variant = 0;
|
|
|
|
// Variant name.
|
|
string Name = "att";
|
|
|
|
// Discard comments in assembly strings.
|
|
string CommentDelimiter = "#";
|
|
|
|
// Recognize hard coded registers.
|
|
string RegisterPrefix = "%";
|
|
}
|
|
|
|
def IntelAsmParserVariant : AsmParserVariant {
|
|
int Variant = 1;
|
|
|
|
// Variant name.
|
|
string Name = "intel";
|
|
|
|
// Discard comments in assembly strings.
|
|
string CommentDelimiter = ";";
|
|
|
|
// Recognize hard coded registers.
|
|
string RegisterPrefix = "";
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly Printers
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// The X86 target supports two different syntaxes for emitting machine code.
|
|
// This is controlled by the -x86-asm-syntax={att|intel}
|
|
def ATTAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "ATTInstPrinter";
|
|
int Variant = 0;
|
|
}
|
|
def IntelAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "IntelInstPrinter";
|
|
int Variant = 1;
|
|
}
|
|
|
|
def X86 : Target {
|
|
// Information about the instructions...
|
|
let InstructionSet = X86InstrInfo;
|
|
let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
|
|
let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
|
|
let AllowRegisterRenaming = 1;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pfm Counters
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "X86PfmCounters.td"
|