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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
82 lines
2.8 KiB
C++
82 lines
2.8 KiB
C++
//===- X86RegisterBankInfo ---------------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the RegisterBankInfo class for X86.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H
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#define LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#define GET_REGBANK_DECLARATIONS
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#include "X86GenRegisterBank.inc"
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namespace llvm {
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class LLT;
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class X86GenRegisterBankInfo : public RegisterBankInfo {
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protected:
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#define GET_TARGET_REGBANK_CLASS
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#include "X86GenRegisterBank.inc"
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#define GET_TARGET_REGBANK_INFO_CLASS
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#include "X86GenRegisterBankInfo.def"
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static RegisterBankInfo::PartialMapping PartMappings[];
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static RegisterBankInfo::ValueMapping ValMappings[];
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static PartialMappingIdx getPartialMappingIdx(const LLT &Ty, bool isFP);
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static const RegisterBankInfo::ValueMapping *
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getValueMapping(PartialMappingIdx Idx, unsigned NumOperands);
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};
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class TargetRegisterInfo;
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/// This class provides the information for the target register banks.
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class X86RegisterBankInfo final : public X86GenRegisterBankInfo {
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private:
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/// Get an instruction mapping.
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/// \return An InstructionMappings with a statically allocated
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/// OperandsMapping.
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const InstructionMapping &getSameOperandsMapping(const MachineInstr &MI,
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bool isFP) const;
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/// Track the bank of each instruction operand(register)
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static void
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getInstrPartialMappingIdxs(const MachineInstr &MI,
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const MachineRegisterInfo &MRI, const bool isFP,
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SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx);
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/// Construct the instruction ValueMapping from PartialMappingIdxs
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/// \return true if mapping succeeded.
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static bool
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getInstrValueMapping(const MachineInstr &MI,
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const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx,
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SmallVectorImpl<const ValueMapping *> &OpdsMapping);
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public:
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X86RegisterBankInfo(const TargetRegisterInfo &TRI);
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const RegisterBank &
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getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
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InstructionMappings
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getInstrAlternativeMappings(const MachineInstr &MI) const override;
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/// See RegisterBankInfo::applyMapping.
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void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
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const InstructionMapping &
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getInstrMapping(const MachineInstr &MI) const override;
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};
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} // namespace llvm
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#endif
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