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0192a1dd5e
`saa` and `saad` are 32-bit and 64-bit store atomic add instructions. memory[base] = memory[base] + rt These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+". Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP` ISA extension flag support. Differential Revision: https://reviews.llvm.org/D69849
11 lines
454 B
ArmAsm
11 lines
454 B
ArmAsm
# Instructions that are invalid.
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#
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# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=octeon+ 2>%t1
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# RUN: FileCheck %s < %t1
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saa $2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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saa $2, $5, $6 # CHECK: :[[@LINE]]:12: error: unexpected token in argument list
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saad $2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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saad $2, $5, $6 # CHECK: :[[@LINE]]:12: error: unexpected token in argument list
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