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6db76aaf10
This is still a work in progress but most of the NEON instruction set is supported. llvm-svn: 73919
18 lines
568 B
LLVM
18 lines
568 B
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
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; RUN: grep {vcnt\\.8} %t | count 2
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define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8> %tmp1)
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ret <16 x i8> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8>) nounwind readnone
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