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bd8f1be276
The custom lowering saves an instruction over the generic expansion, by taking advantage of the fact that PowerPC shift instructions are well defined in the shift-by-bitwidth case. Differential Revision: https://reviews.llvm.org/D83948
64 lines
2.5 KiB
LLVM
64 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
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%struct.m.2.5.8.11 = type { %struct.l.0.3.6.9, [7 x i8], %struct.a.1.4.7.10 }
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%struct.l.0.3.6.9 = type { i8 }
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%struct.a.1.4.7.10 = type { [27 x i8], [0 x i32], [4 x i8] }
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define void @_ZN1m1nEv(%struct.m.2.5.8.11* %this) local_unnamed_addr nounwind align 2 {
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; CHECK-LABEL: _ZN1m1nEv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r0, 16(r1)
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; CHECK-NEXT: stdu r1, -64(r1)
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; CHECK-NEXT: mr r30, r3
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; CHECK-NEXT: li r3, 4
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; CHECK-NEXT: ld r4, 16(r30)
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; CHECK-NEXT: ld r5, 8(r30)
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; CHECK-NEXT: subfic r29, r3, 64
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; CHECK-NEXT: rldicl r3, r5, 60, 4
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; CHECK-NEXT: sld r4, r4, r29
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; CHECK-NEXT: lwz r5, 36(r30)
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; CHECK-NEXT: or r3, r4, r3
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; CHECK-NEXT: rlwinm r3, r3, 31, 0, 0
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; CHECK-NEXT: clrlwi r4, r5, 31
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; CHECK-NEXT: or r4, r4, r3
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; CHECK-NEXT: bl _ZN1llsE1d
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; CHECK-NEXT: nop
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; CHECK-NEXT: ld r3, 16(r30)
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; CHECK-NEXT: ld r4, 8(r30)
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; CHECK-NEXT: rldicl r4, r4, 60, 4
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; CHECK-NEXT: sld r3, r3, r29
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; CHECK-NEXT: or r3, r3, r4
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; CHECK-NEXT: sldi r3, r3, 31
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; CHECK-NEXT: clrldi r4, r3, 32
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; CHECK-NEXT: bl _ZN1llsE1d
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 64
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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entry:
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%bc = getelementptr inbounds %struct.m.2.5.8.11, %struct.m.2.5.8.11* %this, i64 0, i32 2
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%0 = bitcast %struct.a.1.4.7.10* %bc to i216*
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%bf.load = load i216, i216* %0, align 8
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%bf.lshr = lshr i216 %bf.load, 4
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%shl.i23 = shl i216 %bf.lshr, 31
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%shl.i = trunc i216 %shl.i23 to i32
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%arrayidx = getelementptr inbounds %struct.m.2.5.8.11, %struct.m.2.5.8.11* %this, i64 0, i32 2, i32 1, i64 0
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%1 = load i32, i32* %arrayidx, align 4
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%and.i = and i32 %1, 1
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%or.i = or i32 %and.i, %shl.i
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tail call void @_ZN1llsE1d(%struct.l.0.3.6.9* undef, i32 %or.i) #1
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%bf.load10 = load i216, i216* %0, align 8
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%bf.lshr11 = lshr i216 %bf.load10, 4
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%shl.i1524 = shl i216 %bf.lshr11, 31
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%shl.i15 = trunc i216 %shl.i1524 to i32
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tail call void @_ZN1llsE1d(%struct.l.0.3.6.9* undef, i32 %shl.i15) #1
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ret void
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}
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declare void @_ZN1llsE1d(%struct.l.0.3.6.9*, i32) local_unnamed_addr #0
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