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64f3f18f53
Summary: This resolves the issue of tablegen-erated includes in the headers for non-GlobalISel builds in a simpler way than before. Reviewers: qcolombet, ab Reviewed By: ab Subscribers: igorb, ab, mgorny, dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30998 llvm-svn: 299637
79 lines
2.5 KiB
C++
79 lines
2.5 KiB
C++
//==-- AArch64TargetMachine.h - Define TargetMachine for AArch64 -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the AArch64 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETMACHINE_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETMACHINE_H
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#include "AArch64InstrInfo.h"
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#include "AArch64Subtarget.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class AArch64RegisterBankInfo;
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class AArch64TargetMachine : public LLVMTargetMachine {
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protected:
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
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public:
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AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool IsLittleEndian);
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~AArch64TargetMachine() override;
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const AArch64Subtarget *getSubtargetImpl(const Function &F) const override;
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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/// \brief Get the TargetIRAnalysis for this target.
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TargetIRAnalysis getTargetIRAnalysis() override;
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TargetLoweringObjectFile* getObjFileLowering() const override {
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return TLOF.get();
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}
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private:
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bool isLittle;
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};
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// AArch64 little endian target machine.
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//
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class AArch64leTargetMachine : public AArch64TargetMachine {
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virtual void anchor();
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public:
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AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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// AArch64 big endian target machine.
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//
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class AArch64beTargetMachine : public AArch64TargetMachine {
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virtual void anchor();
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public:
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AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // end namespace llvm
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#endif
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