Matt Arsenault 0a495d2b92 AMDGPU/GlobalISel: Fix missing scc imp-def on scalar and/or/xor

2019-12-21 04:55:36 -05:00

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AArch64

[AArch64][SVE] Replace integer immediate intrinsics with splat vector variant

2019-12-20 13:52:19 -05:00

AMDGPU

AMDGPU/GlobalISel: Fix missing scc imp-def on scalar and/or/xor

2019-12-21 04:55:36 -05:00

ARC

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ARM

Revert "[ARM] Improve codegen of volatile load/store of i64"

2019-12-20 18:08:24 +00:00

AVR

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BPF

[BPF] put not-section-attribute externs into BTF ".extern" data section

2019-12-10 11:45:17 -08:00

Generic

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Hexagon

[ModuloSchedule] Fix a bug in experimental expander

2019-11-23 16:01:47 -08:00

Inputs

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Lanai

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Mips

[Mips] Add support for min/max/umin/umax atomics

2019-12-12 11:32:37 +01:00

MIR

[llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands.

2019-12-16 18:25:04 -05:00

MSP430

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NVPTX

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PowerPC

[PPC32] Emit R_PPC_PLTREL24 for calls to dso_local ifunc

2019-12-20 11:32:02 -08:00

RISCV

[RISCV] Enable the machine outliner for RISC-V

2019-12-19 16:41:53 +00:00

SPARC

Temporarily run machine-verifier once in test/CodeGen/SPARC/fp128.ll, so that

2019-12-03 11:21:52 +01:00

SystemZ

[SystemZ] Add a mapping from "select register" to "load on condition" (2-addr).

2019-12-20 10:44:58 -08:00

Thumb

Revert "ARM-Darwin: keep the frame register reserved even if not updated."

2019-12-06 10:59:26 -08:00

Thumb2

[ARM][MVE] Fixes for tail predication.

2019-12-20 09:34:18 +00:00

WebAssembly

[WebAssembly] Add avgr_u intrinsics and require nuw in patterns

2019-12-18 15:31:38 -08:00

WinCFGuard

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WinEH

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X86

[X86] Add test cases for missing propagation of fpexcept flag on strict fp operations. NFC

2019-12-20 15:55:13 -08:00

XCore

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