Jim Grosbach 067a40bdd0 ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane. ... These instructions, such as vmul.f32, require the second source operand to be in D0-D15 rather than the full D0-D31. When optimizing, make sure to account for that by constraining the register class of a replacement virtual register to be compatible with the virtual register(s) it's replacing. I've been unsuccessful in creating a non-fragile regression test. This issue was detected by the LLVM nightly test suite running on an A15 (Bullet). PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093 llvm-svn: 189972		2013-09-04 19:08:44 +00:00
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Analysis
AsmParser
Bitcode
CodeGen	Revert "Revert "Remove the darwin gdb option, that version of gdb is now dead and the rest of the compatibility should be done on a dwarf-N level.""	2013-09-04 04:39:38 +00:00
DebugInfo
ExecutionEngine	llvm interpreter: select, shuffle and insertelement instructions.	2013-09-02 06:40:09 +00:00
IR
IRReader
Linker	Error on linking appending globals with different unnamed_addr.	2013-09-04 15:33:34 +00:00
MC
Object
Option
Support	Move generic isPrint and columnWidth implementations to a separate header/source to allow using both generic and system-dependent versions on win32.	2013-09-04 16:00:12 +00:00
TableGen
Target	ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.	2013-09-04 19:08:44 +00:00
Transforms	Small simplification given that insert of an empty range is a nop.	2013-09-04 18:53:21 +00:00
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LLVMBuild.txt
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