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Summary: Without these patterns we would generate a complete LL/SC sequence. This would be problematic for memory regions marked as WRITE-only or READ-only, as the instructions LL/SC would read/write to the protected memory regions correspondingly. Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14397 llvm-svn: 252293
27 lines
596 B
LLVM
27 lines
596 B
LLVM
; RUN: llc -asm-show-inst -march=mipsel -mcpu=mips32r6 < %s | \
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; RUN: FileCheck %s -check-prefix=CHK32
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; RUN: llc -asm-show-inst -march=mips64el -mcpu=mips64r6 < %s | \
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; RUN: FileCheck %s -check-prefix=CHK64
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@a = common global i32 0, align 4
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@b = common global i64 0, align 8
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define i32 @ll_sc(i32 signext %x) {
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; CHK32-LABEL: ll_sc
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;CHK32: LL_R6
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;CHK32: SC_R6
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%1 = atomicrmw add i32* @a, i32 %x monotonic
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ret i32 %1
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}
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define i64 @lld_scd(i64 signext %x) {
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; CHK64-LABEL: lld_scd
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;CHK64: LLD_R6
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;CHK64: SCD_R6
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%1 = atomicrmw add i64* @b, i64 %x monotonic
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ret i64 %1
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}
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