mirror of
https://github.com/RPCS3/llvm-mirror.git
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dd324fafb5
This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
316 lines
10 KiB
LLVM
316 lines
10 KiB
LLVM
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV \
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; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
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; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV \
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; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV \
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; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV \
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; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
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; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
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define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
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entry:
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; ALL-LABEL: tst_select_i1_double:
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; M2: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: ldc1 $f0, 16($sp)
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; M2: jr $ra
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; M2: nop
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; M2: $[[BB0]]:
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; M2: mtc1 $7, $f0
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; M2: jr $ra
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; M2: mtc1 $6, $f1
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; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]]
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; CMOV-32R1: mtc1 $6, $f{{[0-9]+}}
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; CMOV-32R2-R5: mthc1 $6, $[[F0]]
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; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
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; CMOV-32: ldc1 $f0, 16($sp)
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; CMOV-32: movn.d $f0, $[[F0]], $[[T0]]
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; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
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; SEL-32: mthc1 $6, $[[F0]]
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; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp)
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; SEL-32: mtc1 $4, $f0
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; SEL-32: sel.d $f0, $[[F1]], $[[F0]]
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; M3: andi $[[T0:[0-9]+]], $4, 1
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; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M3: nop
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; M3: mov.d $f13, $f14
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; M3: $[[BB0]]:
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; M3: jr $ra
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; M3: mov.d $f0, $f13
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; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
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; CMOV-64: movn.d $f14, $f13, $[[T0]]
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; CMOV-64: mov.d $f0, $f14
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; SEL-64: mtc1 $4, $f0
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; SEL-64: sel.d $f0, $f14, $f13
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%r = select i1 %s, double %x, double %y
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ret double %r
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}
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define double @tst_select_i1_double_reordered(double %x, double %y,
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i1 signext %s) {
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entry:
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; ALL-LABEL: tst_select_i1_double_reordered:
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; M2: lw $[[T0:[0-9]+]], 16($sp)
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; M2: andi $[[T1:[0-9]+]], $[[T0]], 1
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; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: mov.d $f12, $f14
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: mov.d $f0, $f12
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; CMOV-32: lw $[[T0:[0-9]+]], 16($sp)
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; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1
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; CMOV-32: movn.d $f14, $f12, $[[T1]]
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; CMOV-32: mov.d $f0, $f14
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; SEL-32: lw $[[T0:[0-9]+]], 16($sp)
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; SEL-32: mtc1 $[[T0]], $f0
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; SEL-32: sel.d $f0, $f14, $f12
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; M3: andi $[[T0:[0-9]+]], $6, 1
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; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M3: nop
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; M3: mov.d $f12, $f13
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; M3: $[[BB0]]:
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; M3: jr $ra
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; M3: mov.d $f0, $f12
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; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
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; CMOV-64: movn.d $f13, $f12, $[[T0]]
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; CMOV-64: mov.d $f0, $f13
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; SEL-64: mtc1 $6, $f0
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; SEL-64: sel.d $f0, $f13, $f12
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%r = select i1 %s, double %x, double %y
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ret double %r
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}
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define double @tst_select_fcmp_olt_double(double %x, double %y) {
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entry:
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; ALL-LABEL: tst_select_fcmp_olt_double:
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; M2: c.olt.d $f12, $f14
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; M3: c.olt.d $f12, $f13
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; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.d $f12, $f14
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; M3: mov.d $f12, $f13
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: mov.d $f0, $f12
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; CMOV-32: c.olt.d $f12, $f14
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; CMOV-32: movt.d $f14, $f12, $fcc0
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; CMOV-32: mov.d $f0, $f14
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; SEL-32: cmp.lt.d $f0, $f12, $f14
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; SEL-32: sel.d $f0, $f14, $f12
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; CMOV-64: c.olt.d $f12, $f13
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; CMOV-64: movt.d $f13, $f12, $fcc0
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; CMOV-64: mov.d $f0, $f13
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; SEL-64: cmp.lt.d $f0, $f12, $f13
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; SEL-64: sel.d $f0, $f13, $f12
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%s = fcmp olt double %x, %y
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%r = select i1 %s, double %x, double %y
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ret double %r
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}
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define double @tst_select_fcmp_ole_double(double %x, double %y) {
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entry:
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; ALL-LABEL: tst_select_fcmp_ole_double:
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; M2: c.ole.d $f12, $f14
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; M3: c.ole.d $f12, $f13
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; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.d $f12, $f14
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; M3: mov.d $f12, $f13
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: mov.d $f0, $f12
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; CMOV-32: c.ole.d $f12, $f14
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; CMOV-32: movt.d $f14, $f12, $fcc0
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; CMOV-32: mov.d $f0, $f14
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; SEL-32: cmp.le.d $f0, $f12, $f14
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; SEL-32: sel.d $f0, $f14, $f12
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; CMOV-64: c.ole.d $f12, $f13
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; CMOV-64: movt.d $f13, $f12, $fcc0
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; CMOV-64: mov.d $f0, $f13
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; SEL-64: cmp.le.d $f0, $f12, $f13
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; SEL-64: sel.d $f0, $f13, $f12
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%s = fcmp ole double %x, %y
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%r = select i1 %s, double %x, double %y
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ret double %r
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}
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define double @tst_select_fcmp_ogt_double(double %x, double %y) {
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entry:
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; ALL-LABEL: tst_select_fcmp_ogt_double:
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; M2: c.ule.d $f12, $f14
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; M3: c.ule.d $f12, $f13
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; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.d $f12, $f14
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; M3: mov.d $f12, $f13
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: mov.d $f0, $f12
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; CMOV-32: c.ule.d $f12, $f14
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; CMOV-32: movf.d $f14, $f12, $fcc0
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; CMOV-32: mov.d $f0, $f14
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; SEL-32: cmp.lt.d $f0, $f14, $f12
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; SEL-32: sel.d $f0, $f14, $f12
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; CMOV-64: c.ule.d $f12, $f13
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; CMOV-64: movf.d $f13, $f12, $fcc0
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; CMOV-64: mov.d $f0, $f13
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; SEL-64: cmp.lt.d $f0, $f13, $f12
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; SEL-64: sel.d $f0, $f13, $f12
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%s = fcmp ogt double %x, %y
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%r = select i1 %s, double %x, double %y
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ret double %r
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}
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define double @tst_select_fcmp_oge_double(double %x, double %y) {
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entry:
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; ALL-LABEL: tst_select_fcmp_oge_double:
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; M2: c.ult.d $f12, $f14
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; M3: c.ult.d $f12, $f13
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; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.d $f12, $f14
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; M3: mov.d $f12, $f13
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: mov.d $f0, $f12
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; CMOV-32: c.ult.d $f12, $f14
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; CMOV-32: movf.d $f14, $f12, $fcc0
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; CMOV-32: mov.d $f0, $f14
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; SEL-32: cmp.le.d $f0, $f14, $f12
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; SEL-32: sel.d $f0, $f14, $f12
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; CMOV-64: c.ult.d $f12, $f13
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; CMOV-64: movf.d $f13, $f12, $fcc0
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; CMOV-64: mov.d $f0, $f13
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; SEL-64: cmp.le.d $f0, $f13, $f12
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; SEL-64: sel.d $f0, $f13, $f12
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%s = fcmp oge double %x, %y
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%r = select i1 %s, double %x, double %y
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ret double %r
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}
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define double @tst_select_fcmp_oeq_double(double %x, double %y) {
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entry:
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; ALL-LABEL: tst_select_fcmp_oeq_double:
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; M2: c.eq.d $f12, $f14
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; M3: c.eq.d $f12, $f13
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; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.d $f12, $f14
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; M3: mov.d $f12, $f13
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: mov.d $f0, $f12
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; CMOV-32: c.eq.d $f12, $f14
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; CMOV-32: movt.d $f14, $f12, $fcc0
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; CMOV-32: mov.d $f0, $f14
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; SEL-32: cmp.eq.d $f0, $f12, $f14
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; SEL-32: sel.d $f0, $f14, $f12
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; CMOV-64: c.eq.d $f12, $f13
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; CMOV-64: movt.d $f13, $f12, $fcc0
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; CMOV-64: mov.d $f0, $f13
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; SEL-64: cmp.eq.d $f0, $f12, $f13
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; SEL-64: sel.d $f0, $f13, $f12
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%s = fcmp oeq double %x, %y
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%r = select i1 %s, double %x, double %y
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ret double %r
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}
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define double @tst_select_fcmp_one_double(double %x, double %y) {
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entry:
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; ALL-LABEL: tst_select_fcmp_one_double:
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; M2: c.ueq.d $f12, $f14
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; M3: c.ueq.d $f12, $f13
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; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.d $f12, $f14
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; M3: mov.d $f12, $f13
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: mov.d $f0, $f12
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; CMOV-32: c.ueq.d $f12, $f14
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; CMOV-32: movf.d $f14, $f12, $fcc0
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; CMOV-32: mov.d $f0, $f14
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; SEL-32: cmp.ueq.d $f0, $f12, $f14
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; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
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; SEL-32: not $[[T0]], $[[T0]]
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; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
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; SEL-32: sel.d $f0, $f14, $f12
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; CMOV-64: c.ueq.d $f12, $f13
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; CMOV-64: movf.d $f13, $f12, $fcc0
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; CMOV-64: mov.d $f0, $f13
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; SEL-64: cmp.ueq.d $f0, $f12, $f13
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; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
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; SEL-64: not $[[T0]], $[[T0]]
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; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
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; SEL-64: sel.d $f0, $f13, $f12
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%s = fcmp one double %x, %y
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%r = select i1 %s, double %x, double %y
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ret double %r
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}
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