mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 03:33:20 +01:00
ab043ff680
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
95 lines
3.4 KiB
LLVM
95 lines
3.4 KiB
LLVM
; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction
|
|
; format.
|
|
|
|
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
|
|
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
|
|
|
@llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
|
|
@llvm_mips_mul_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
|
|
@llvm_mips_mul_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
|
|
|
|
define void @llvm_mips_mul_q_h_test() nounwind {
|
|
entry:
|
|
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_mul_q_h_ARG1
|
|
%1 = load <8 x i16>, <8 x i16>* @llvm_mips_mul_q_h_ARG2
|
|
%2 = tail call <8 x i16> @llvm.mips.mul.q.h(<8 x i16> %0, <8 x i16> %1)
|
|
store <8 x i16> %2, <8 x i16>* @llvm_mips_mul_q_h_RES
|
|
ret void
|
|
}
|
|
|
|
declare <8 x i16> @llvm.mips.mul.q.h(<8 x i16>, <8 x i16>) nounwind
|
|
|
|
; CHECK: llvm_mips_mul_q_h_test:
|
|
; CHECK: ld.h
|
|
; CHECK: ld.h
|
|
; CHECK: mul_q.h
|
|
; CHECK: st.h
|
|
; CHECK: .size llvm_mips_mul_q_h_test
|
|
;
|
|
@llvm_mips_mul_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
|
@llvm_mips_mul_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
|
|
@llvm_mips_mul_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
|
|
|
|
define void @llvm_mips_mul_q_w_test() nounwind {
|
|
entry:
|
|
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_mul_q_w_ARG1
|
|
%1 = load <4 x i32>, <4 x i32>* @llvm_mips_mul_q_w_ARG2
|
|
%2 = tail call <4 x i32> @llvm.mips.mul.q.w(<4 x i32> %0, <4 x i32> %1)
|
|
store <4 x i32> %2, <4 x i32>* @llvm_mips_mul_q_w_RES
|
|
ret void
|
|
}
|
|
|
|
declare <4 x i32> @llvm.mips.mul.q.w(<4 x i32>, <4 x i32>) nounwind
|
|
|
|
; CHECK: llvm_mips_mul_q_w_test:
|
|
; CHECK: ld.w
|
|
; CHECK: ld.w
|
|
; CHECK: mul_q.w
|
|
; CHECK: st.w
|
|
; CHECK: .size llvm_mips_mul_q_w_test
|
|
;
|
|
@llvm_mips_mulr_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
|
|
@llvm_mips_mulr_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
|
|
@llvm_mips_mulr_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
|
|
|
|
define void @llvm_mips_mulr_q_h_test() nounwind {
|
|
entry:
|
|
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_mulr_q_h_ARG1
|
|
%1 = load <8 x i16>, <8 x i16>* @llvm_mips_mulr_q_h_ARG2
|
|
%2 = tail call <8 x i16> @llvm.mips.mulr.q.h(<8 x i16> %0, <8 x i16> %1)
|
|
store <8 x i16> %2, <8 x i16>* @llvm_mips_mulr_q_h_RES
|
|
ret void
|
|
}
|
|
|
|
declare <8 x i16> @llvm.mips.mulr.q.h(<8 x i16>, <8 x i16>) nounwind
|
|
|
|
; CHECK: llvm_mips_mulr_q_h_test:
|
|
; CHECK: ld.h
|
|
; CHECK: ld.h
|
|
; CHECK: mulr_q.h
|
|
; CHECK: st.h
|
|
; CHECK: .size llvm_mips_mulr_q_h_test
|
|
;
|
|
@llvm_mips_mulr_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
|
@llvm_mips_mulr_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
|
|
@llvm_mips_mulr_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
|
|
|
|
define void @llvm_mips_mulr_q_w_test() nounwind {
|
|
entry:
|
|
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_mulr_q_w_ARG1
|
|
%1 = load <4 x i32>, <4 x i32>* @llvm_mips_mulr_q_w_ARG2
|
|
%2 = tail call <4 x i32> @llvm.mips.mulr.q.w(<4 x i32> %0, <4 x i32> %1)
|
|
store <4 x i32> %2, <4 x i32>* @llvm_mips_mulr_q_w_RES
|
|
ret void
|
|
}
|
|
|
|
declare <4 x i32> @llvm.mips.mulr.q.w(<4 x i32>, <4 x i32>) nounwind
|
|
|
|
; CHECK: llvm_mips_mulr_q_w_test:
|
|
; CHECK: ld.w
|
|
; CHECK: ld.w
|
|
; CHECK: mulr_q.w
|
|
; CHECK: st.w
|
|
; CHECK: .size llvm_mips_mulr_q_w_test
|
|
;
|