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8f83ef0f5e
Patch [4/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions. We add SVE as unsupported feature for CPUs that don't have SVE to prevent errors from scheduler models saying it lacks information for these instructions. Patch by Sander De Smalen. Reviewed by: rengolin Differential Revision: https://reviews.llvm.org/D39090 llvm-svn: 317582
117 lines
5.1 KiB
TableGen
117 lines
5.1 KiB
TableGen
//==- AArch64SchedFalkor.td - Falkor Scheduling Definitions -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for Qualcomm Falkor to support
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// instruction scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Define the SchedMachineModel and provide basic properties for coarse grained
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// instruction cost model.
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def FalkorModel : SchedMachineModel {
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let IssueWidth = 8; // 8 uops are dispatched per cycle.
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let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.
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let LoopMicroOpBufferSize = 16;
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let LoadLatency = 3; // Optimistic load latency.
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let MispredictPenalty = 11; // Minimum branch misprediction penalty.
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let CompleteModel = 1;
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list<Predicate> UnsupportedFeatures = [HasSVE];
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}
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//===----------------------------------------------------------------------===//
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// Define each kind of processor resource and number available on Falkor.
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let SchedModel = FalkorModel in {
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def FalkorUnitB : ProcResource<1>; // Branch
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def FalkorUnitLD : ProcResource<1>; // Load pipe
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def FalkorUnitSD : ProcResource<1>; // Store data
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def FalkorUnitST : ProcResource<1>; // Store pipe
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def FalkorUnitX : ProcResource<1>; // Complex arithmetic
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def FalkorUnitY : ProcResource<1>; // Simple arithmetic
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def FalkorUnitZ : ProcResource<1>; // Simple arithmetic
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def FalkorUnitVSD : ProcResource<1>; // Vector store data
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def FalkorUnitVX : ProcResource<1>; // Vector X-pipe
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def FalkorUnitVY : ProcResource<1>; // Vector Y-pipe
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def FalkorUnitGTOV : ProcResource<1>; // Scalar to Vector
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def FalkorUnitVTOG : ProcResource<1>; // Vector to Scalar
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// Define the resource groups.
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def FalkorUnitXY : ProcResGroup<[FalkorUnitX, FalkorUnitY]>;
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def FalkorUnitXYZ : ProcResGroup<[FalkorUnitX, FalkorUnitY, FalkorUnitZ]>;
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def FalkorUnitXYZB : ProcResGroup<[FalkorUnitX, FalkorUnitY, FalkorUnitZ,
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FalkorUnitB]>;
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def FalkorUnitZB : ProcResGroup<[FalkorUnitZ, FalkorUnitB]>;
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def FalkorUnitVXVY : ProcResGroup<[FalkorUnitVX, FalkorUnitVY]>;
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}
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//===----------------------------------------------------------------------===//
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// Map the target-defined scheduler read/write resources and latency for
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// Falkor.
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let SchedModel = FalkorModel in {
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// These WriteRes entries are not used in the Falkor sched model.
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def : WriteRes<WriteImm, []> { let Unsupported = 1; }
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def : WriteRes<WriteI, []> { let Unsupported = 1; }
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def : WriteRes<WriteISReg, []> { let Unsupported = 1; }
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def : WriteRes<WriteIEReg, []> { let Unsupported = 1; }
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def : WriteRes<WriteExtr, []> { let Unsupported = 1; }
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def : WriteRes<WriteIS, []> { let Unsupported = 1; }
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def : WriteRes<WriteID32, []> { let Unsupported = 1; }
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def : WriteRes<WriteID64, []> { let Unsupported = 1; }
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def : WriteRes<WriteIM32, []> { let Unsupported = 1; }
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def : WriteRes<WriteIM64, []> { let Unsupported = 1; }
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def : WriteRes<WriteBr, []> { let Unsupported = 1; }
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def : WriteRes<WriteBrReg, []> { let Unsupported = 1; }
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def : WriteRes<WriteLD, []> { let Unsupported = 1; }
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def : WriteRes<WriteST, []> { let Unsupported = 1; }
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def : WriteRes<WriteSTP, []> { let Unsupported = 1; }
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def : WriteRes<WriteAdr, []> { let Unsupported = 1; }
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def : WriteRes<WriteLDIdx, []> { let Unsupported = 1; }
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def : WriteRes<WriteSTIdx, []> { let Unsupported = 1; }
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def : WriteRes<WriteF, []> { let Unsupported = 1; }
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def : WriteRes<WriteFCmp, []> { let Unsupported = 1; }
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def : WriteRes<WriteFCvt, []> { let Unsupported = 1; }
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def : WriteRes<WriteFCopy, []> { let Unsupported = 1; }
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def : WriteRes<WriteFImm, []> { let Unsupported = 1; }
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def : WriteRes<WriteFMul, []> { let Unsupported = 1; }
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def : WriteRes<WriteFDiv, []> { let Unsupported = 1; }
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def : WriteRes<WriteV, []> { let Unsupported = 1; }
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def : WriteRes<WriteVLD, []> { let Unsupported = 1; }
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def : WriteRes<WriteVST, []> { let Unsupported = 1; }
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def : WriteRes<WriteSys, []> { let Unsupported = 1; }
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def : WriteRes<WriteBarrier, []> { let Unsupported = 1; }
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def : WriteRes<WriteHint, []> { let Unsupported = 1; }
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def : WriteRes<WriteLDHi, []> { let Unsupported = 1; }
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def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
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// These ReadAdvance entries are not used in the Falkor sched model.
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def : ReadAdvance<ReadI, 0>;
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def : ReadAdvance<ReadISReg, 0>;
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def : ReadAdvance<ReadIEReg, 0>;
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def : ReadAdvance<ReadIM, 0>;
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def : ReadAdvance<ReadIMA, 0>;
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def : ReadAdvance<ReadID, 0>;
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def : ReadAdvance<ReadExtrHi, 0>;
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def : ReadAdvance<ReadAdrBase, 0>;
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def : ReadAdvance<ReadVLD, 0>;
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// Detailed Refinements
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// -----------------------------------------------------------------------------
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include "AArch64SchedFalkorDetails.td"
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}
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