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7f59505011
In Thumb1, legal imm range is [0, 255] for ADD/SUB instructions. However, the legal imm range for LD/ST in (R+Imm) addressing mode is [0, 127]. Imms in [128, 255] are materialized by mov R, #imm, and LD/STs use them in (R+R) addressing mode. This patch checks if a constant is used as offset in (R+Imm), if so, it checks isLegalAddressingMode passing the constant value as BaseOffset. Differential Revision: https://reviews.llvm.org/D50931 llvm-svn: 340882
121 lines
5.5 KiB
LLVM
121 lines
5.5 KiB
LLVM
; RUN: opt -consthoist -S -o - %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv6m-none--musleabi"
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; Check that for i8 type, the maximum legal offset is 31.
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; Also check that an constant used as value to be stored rather than
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; pointer in a store instruction is hoisted.
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; CHECK: foo_i8
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; CHECK-DAG: %[[C1:const[0-9]?]] = bitcast i32 805874720 to i32
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; CHECK-DAG: %[[C2:const[0-9]?]] = bitcast i32 805874688 to i32
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; CHECK-DAG: %[[C3:const[0-9]?]] = bitcast i32 805873720 to i32
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; CHECK-DAG: %[[C4:const[0-9]?]] = bitcast i32 805873688 to i32
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; CHECK: %0 = inttoptr i32 %[[C2]] to i8*
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; CHECK-NEXT: %1 = load volatile i8, i8* %0
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; CHECK-NEXT: %[[M1:const_mat[0-9]?]] = add i32 %[[C2]], 4
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; CHECK-NEXT: %2 = inttoptr i32 %[[M1]] to i8*
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; CHECK-NEXT: %3 = load volatile i8, i8* %2
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; CHECK-NEXT: %[[M2:const_mat[0-9]?]] = add i32 %[[C2]], 31
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; CHECK-NEXT: %4 = inttoptr i32 %[[M2]] to i8*
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; CHECK-NEXT: %5 = load volatile i8, i8* %4
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; CHECK-NEXT: %6 = inttoptr i32 %[[C1]] to i8*
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; CHECK-NEXT: %7 = load volatile i8, i8* %6
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; CHECK-NEXT: %[[M3:const_mat[0-9]?]] = add i32 %[[C1]], 7
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; CHECK-NEXT: %8 = inttoptr i32 %[[M3]] to i8*
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; CHECK-NEXT: %9 = load volatile i8, i8* %8
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; CHECK-NEXT: %10 = inttoptr i32 %[[C4]] to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: %[[M4:const_mat[0-9]?]] = add i32 %[[C4]], 31
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; CHECK-NEXT: %11 = inttoptr i32 %[[M4]] to i8*
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; CHECK-NEXT: store i8 %7, i8* %11
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; CHECK-NEXT: %12 = inttoptr i32 %[[C3]] to i8*
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; CHECK-NEXT: store i8 %5, i8* %12
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; CHECK-NEXT: %[[M5:const_mat[0-9]?]] = add i32 %[[C3]], 7
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; CHECK-NEXT: %13 = inttoptr i32 %[[M5]] to i8*
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; CHECK-NEXT: store i8 %3, i8* %13
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; CHECK-NEXT: %[[M6:const_mat[0-9]?]] = add i32 %[[C1]], 80
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; CHECK-NEXT: %14 = inttoptr i32 %[[M6]] to i8*
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; CHECK-NEXT: store i8* %14, i8** @goo
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@goo = global i8* undef
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define void @foo_i8() {
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entry:
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%0 = load volatile i8, i8* inttoptr (i32 805874688 to i8*)
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%1 = load volatile i8, i8* inttoptr (i32 805874692 to i8*)
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%2 = load volatile i8, i8* inttoptr (i32 805874719 to i8*)
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%3 = load volatile i8, i8* inttoptr (i32 805874720 to i8*)
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%4 = load volatile i8, i8* inttoptr (i32 805874727 to i8*)
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store i8 %4, i8* inttoptr(i32 805873688 to i8*)
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store i8 %3, i8* inttoptr(i32 805873719 to i8*)
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store i8 %2, i8* inttoptr(i32 805873720 to i8*)
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store i8 %1, i8* inttoptr(i32 805873727 to i8*)
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store i8* inttoptr(i32 805874800 to i8*), i8** @goo
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ret void
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}
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; Check that for i16 type, the maximum legal offset is 62.
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; CHECK: foo_i16
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; CHECK-DAG: %[[C1:const[0-9]?]] = bitcast i32 805874752 to i32
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; CHECK-DAG: %[[C2:const[0-9]?]] = bitcast i32 805874688 to i32
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; CHECK: %0 = inttoptr i32 %[[C2]] to i16*
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; CHECK-NEXT: %1 = load volatile i16, i16* %0, align 2
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; CHECK-NEXT: %[[M1:const_mat[0-9]?]] = add i32 %[[C2]], 4
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; CHECK-NEXT: %2 = inttoptr i32 %[[M1]] to i16*
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; CHECK-NEXT: %3 = load volatile i16, i16* %2, align 2
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; CHECK-NEXT: %[[M2:const_mat[0-9]?]] = add i32 %[[C2]], 32
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; CHECK-NEXT: %4 = inttoptr i32 %[[M2]] to i16*
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; CHECK-NEXT: %5 = load volatile i16, i16* %4, align 2
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; CHECK-NEXT: %[[M3:const_mat[0-9]?]] = add i32 %[[C2]], 62
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; CHECK-NEXT: %6 = inttoptr i32 %[[M3]] to i16*
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; CHECK-NEXT: %7 = load volatile i16, i16* %6, align 2
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; CHECK-NEXT: %8 = inttoptr i32 %[[C1]] to i16*
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; CHECK-NEXT: %9 = load volatile i16, i16* %8, align 2
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; CHECK-NEXT: %[[M4:const_mat[0-9]?]] = add i32 %[[C1]], 22
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; CHECK-NEXT: %10 = inttoptr i32 %[[M4]] to i16*
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; CHECK-NEXT: %11 = load volatile i16, i16* %10, align 2
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define void @foo_i16() {
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entry:
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%0 = load volatile i16, i16* inttoptr (i32 805874688 to i16*), align 2
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%1 = load volatile i16, i16* inttoptr (i32 805874692 to i16*), align 2
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%2 = load volatile i16, i16* inttoptr (i32 805874720 to i16*), align 2
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%3 = load volatile i16, i16* inttoptr (i32 805874750 to i16*), align 2
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%4 = load volatile i16, i16* inttoptr (i32 805874752 to i16*), align 2
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%5 = load volatile i16, i16* inttoptr (i32 805874774 to i16*), align 2
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ret void
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}
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; Check that for i32 type, the maximum legal offset is 124.
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; CHECK: foo_i32
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; CHECK-DAG: %[[C1:const[0-9]?]] = bitcast i32 805874816 to i32
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; CHECK-DAG: %[[C2:const[0-9]?]] = bitcast i32 805874688 to i32
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; CHECK: %0 = inttoptr i32 %[[C2]] to i32*
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; CHECK-NEXT: %1 = load volatile i32, i32* %0, align 4
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; CHECK-NEXT: %[[M1:const_mat[0-9]?]] = add i32 %[[C2]], 4
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; CHECK-NEXT: %2 = inttoptr i32 %[[M1]] to i32*
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; CHECK-NEXT: %3 = load volatile i32, i32* %2, align 4
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; CHECK-NEXT: %[[M2:const_mat[0-9]?]] = add i32 %[[C2]], 124
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; CHECK-NEXT: %4 = inttoptr i32 %[[M2]] to i32*
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; CHECK-NEXT: %5 = load volatile i32, i32* %4, align 4
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; CHECK-NEXT: %6 = inttoptr i32 %[[C1]] to i32*
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; CHECK-NEXT: %7 = load volatile i32, i32* %6, align 4
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; CHECK-NEXT: %[[M3:const_mat[0-9]?]] = add i32 %[[C1]], 8
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; CHECK-NEXT: %8 = inttoptr i32 %[[M3]] to i32*
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; CHECK-NEXT: %9 = load volatile i32, i32* %8, align 4
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; CHECK-NEXT: %[[M4:const_mat[0-9]?]] = add i32 %[[C1]], 12
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; CHECK-NEXT: %10 = inttoptr i32 %[[M4]] to i32*
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; CHECK-NEXT: %11 = load volatile i32, i32* %10, align 4
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define void @foo_i32() {
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entry:
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%0 = load volatile i32, i32* inttoptr (i32 805874688 to i32*), align 4
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%1 = load volatile i32, i32* inttoptr (i32 805874692 to i32*), align 4
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%2 = load volatile i32, i32* inttoptr (i32 805874812 to i32*), align 4
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%3 = load volatile i32, i32* inttoptr (i32 805874816 to i32*), align 4
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%4 = load volatile i32, i32* inttoptr (i32 805874824 to i32*), align 4
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%5 = load volatile i32, i32* inttoptr (i32 805874828 to i32*), align 4
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ret void
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}
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