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59948ba101
Summary: Subregister liveness tracking is not implemented for X86 backend, so sometimes the whole super register is said to be live, when only a subregister is really live. That might happen if the def and the use are located in different MBBs, see added fixup-bw-isnt.mir test. However, using knowledge of the specific instructions handled by the bw-fixup-pass we can get more precise liveness information which this change does. Reviewers: MatzeB, DavidKreitzer, ab, andrew.w.kaylor, craig.topper Reviewed By: craig.topper Subscribers: n.bozhenov, myatsina, llvm-commits, hiraditya Patch by Andrei Elovikov <andrei.elovikov@intel.com> Differential Revision: https://reviews.llvm.org/D37559 llvm-svn: 313524
37 lines
1.1 KiB
LLVM
37 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.12.0"
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@a = common local_unnamed_addr global i16 0, align 4
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@b = common local_unnamed_addr global i16 0, align 4
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define i32 @PR32420() {
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; CHECK-LABEL: PR32420:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movq _a@{{.*}}(%rip), %rax
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; CHECK-NEXT: movzwl (%rax), %eax
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shll $12, %ecx
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; CHECK-NEXT: sarw $12, %cx
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; CHECK-NEXT: movq _b@{{.*}}(%rip), %rdx
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; CHECK-NEXT: movl %ecx, %esi
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; CHECK-NEXT: orw (%rdx), %si
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; CHECK-NEXT: andl %ecx, %esi
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; CHECK-NEXT: movw %si, (%rdx)
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; CHECK-NEXT: retq
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%load2 = load i16, i16* @a, align 4
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%shl3 = shl i16 %load2, 12
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%ashr4 = ashr i16 %shl3, 12
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%t2 = load volatile i16, i16* @b, align 4
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%conv8 = or i16 %t2, %ashr4
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%load9 = load i16, i16* @a, align 4
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%shl10 = shl i16 %load9, 12
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%ashr11 = ashr i16 %shl10, 12
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%and = and i16 %conv8, %ashr11
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store i16 %and, i16* @b, align 4
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%cast1629 = zext i16 %load2 to i32
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ret i32 %cast1629
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}
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