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ab043ff680
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
110 lines
3.3 KiB
LLVM
110 lines
3.3 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=core2 -x86-early-ifcvt -enable-misched \
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; RUN: -misched=shuffle -misched-bottomup -verify-machineinstrs \
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; RUN: | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=core2 -x86-early-ifcvt -enable-misched \
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; RUN: -misched=shuffle -misched-topdown -verify-machineinstrs \
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; RUN: | FileCheck %s --check-prefix TOPDOWN
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; REQUIRES: asserts
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;
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; Interesting MachineScheduler cases.
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;
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; FIXME: There should be an assert in the coalescer that we're not rematting
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; "not-quite-dead" copies, but that breaks a lot of tests <rdar://problem/11148682>.
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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; From oggenc.
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; After coalescing, we have a dead superreg (RAX) definition.
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;
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; CHECK: xorl %esi, %esi
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; CHECK: movl $32, %ecx
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; CHECK: rep;movsl
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define fastcc void @_preextrapolate_helper() nounwind uwtable ssp {
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entry:
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br i1 undef, label %for.cond.preheader, label %if.end
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for.cond.preheader: ; preds = %entry
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* null, i64 128, i32 4, i1 false) nounwind
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unreachable
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if.end: ; preds = %entry
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ret void
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}
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; The machine verifier checks that EFLAGS kill flags are updated when
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; the scheduler reorders cmovel instructions.
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;
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; CHECK: test
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; CHECK: cmovel
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; CHECK: cmovel
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; CHECK: call
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define void @foo(i32 %b) nounwind uwtable ssp {
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entry:
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%tobool = icmp ne i32 %b, 0
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br i1 %tobool, label %if.then, label %if.end
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if.then: ; preds = %entry
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br label %if.end
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if.end: ; preds = %if.then, %entry
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%v1 = phi i32 [1, %entry], [2, %if.then]
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%v2 = phi i32 [3, %entry], [4, %if.then]
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call void @bar(i32 %v1, i32 %v2)
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ret void
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}
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declare void @bar(i32,i32)
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; Test that the DAG builder can handle an undef vreg on ExitSU.
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; CHECK: hasundef
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; CHECK: call
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%t0 = type { i32, i32, i8 }
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%t6 = type { i32 (...)**, %t7* }
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%t7 = type { i32 (...)** }
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define void @hasundef() unnamed_addr uwtable ssp align 2 {
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%1 = alloca %t0, align 8
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br i1 undef, label %3, label %2
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; <label>:2 ; preds = %0
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unreachable
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; <label>:3 ; preds = %0
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br i1 undef, label %4, label %5
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; <label>:4 ; preds = %3
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call void undef(%t6* undef, %t0* %1)
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unreachable
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; <label>:5 ; preds = %3
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ret void
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}
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; Test top-down subregister liveness tracking. Self-verification
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; catches any pressure set underflow.
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; rdar://12797931.
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;
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; TOPDOWN: @testSubregTracking
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; TOPDOWN: divb
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; TOPDOWN: movzbl %al
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; TOPDOWN: ret
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define void @testSubregTracking() nounwind uwtable ssp align 2 {
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%tmp = load i8, i8* undef, align 1
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%tmp6 = sub i8 0, %tmp
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%tmp7 = load i8, i8* undef, align 1
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%tmp8 = udiv i8 %tmp6, %tmp7
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%tmp9 = zext i8 %tmp8 to i64
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%tmp10 = load i8, i8* undef, align 1
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%tmp11 = zext i8 %tmp10 to i64
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%tmp12 = mul i64 %tmp11, %tmp9
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%tmp13 = urem i8 %tmp6, %tmp7
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%tmp14 = zext i8 %tmp13 to i32
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%tmp15 = add nsw i32 %tmp14, 0
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%tmp16 = add i32 %tmp15, 0
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store i32 %tmp16, i32* undef, align 4
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%tmp17 = add i64 0, %tmp12
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store i64 %tmp17, i64* undef, align 8
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ret void
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}
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