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98be3942ed
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. llvm-svn: 216225
69 lines
1.5 KiB
LLVM
69 lines
1.5 KiB
LLVM
; RUN: llc -O0 -verify-machineinstrs -mtriple=aarch64-apple-ios < %s | FileCheck %s
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; Fast-isel can't do vector conversions yet, but it was emitting some highly
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; suspect UCVTFUWDri MachineInstrs.
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define <4 x float> @test_uitofp(<4 x i32> %in) {
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; CHECK-LABEL: test_uitofp:
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; CHECK: ucvtf.4s v0, v0
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%res = uitofp <4 x i32> %in to <4 x float>
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ret <4 x float> %res
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}
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define <2 x double> @test_sitofp(<2 x i32> %in) {
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; CHECK-LABEL: test_sitofp:
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; CHECK: sshll.2d [[EXT:v[0-9]+]], v0, #0
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; CHECK: scvtf.2d v0, [[EXT]]
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%res = sitofp <2 x i32> %in to <2 x double>
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ret <2 x double> %res
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}
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define <2 x i32> @test_fptoui(<2 x float> %in) {
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; CHECK-LABEL: test_fptoui:
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; CHECK: fcvtzu.2s v0, v0
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%res = fptoui <2 x float> %in to <2 x i32>
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ret <2 x i32> %res
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}
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define <2 x i64> @test_fptosi(<2 x double> %in) {
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; CHECK-LABEL: test_fptosi:
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; CHECK: fcvtzs.2d v0, v0
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%res = fptosi <2 x double> %in to <2 x i64>
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ret <2 x i64> %res
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}
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define fp128 @uitofp_i32_fp128(i32 %a) {
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entry:
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; CHECK-LABEL: uitofp_i32_fp128
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; CHECK: bl ___floatunsitf
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%conv = uitofp i32 %a to fp128
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ret fp128 %conv
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}
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define fp128 @uitofp_i64_fp128(i64 %a) {
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entry:
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; CHECK-LABEL: uitofp_i64_fp128
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; CHECK: bl ___floatunditf
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%conv = uitofp i64 %a to fp128
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ret fp128 %conv
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}
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define i32 @uitofp_fp128_i32(fp128 %a) {
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entry:
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; CHECK-LABEL: uitofp_fp128_i32
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; CHECK: ___fixunstfsi
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%conv = fptoui fp128 %a to i32
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ret i32 %conv
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}
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define i64 @uitofp_fp128_i64(fp128 %a) {
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entry:
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; CHECK-LABEL: uitofp_fp128_i64
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; CHECK: ___fixunstfdi
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%conv = fptoui fp128 %a to i64
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ret i64 %conv
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}
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