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53ed9373bc
This avoids a partial false dependency on the previous content of the upper lanes of the destination vector register. Differential Revision: http://reviews.llvm.org/D7307 llvm-svn: 227820
16 lines
641 B
LLVM
16 lines
641 B
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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; DAGCombine to transform a conversion of an extract_vector_elt to an
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; extract_vector_elt of a conversion, which saves a round trip of copies
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; of the value to a GPR and back to and FPR.
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; rdar://11855286
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define double @foo0(<2 x i64> %a) nounwind {
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; CHECK: scvtf.2d [[REG:v[0-9]+]], v0, #9
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; CHECK-NEXT: mov d0, [[REG]][1]
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%vecext = extractelement <2 x i64> %a, i32 1
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%fcvt_n = tail call double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64 %vecext, i32 9)
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ret double %fcvt_n
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}
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declare double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64, i32) nounwind readnone
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