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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
llvm-mirror/test/CodeGen
Craig Topper ae6deb0659 [RISCV] Cleanup some V intrinsic names used in tests to match the type overloads used. Add some missing double tests on rv32. NFC
The matching for intrinsic names is forgiving about types in the
name being absent or wrong. Once the intrinsic is parsed its
name will remangled to include the real types.

This commit fixes the names to have at least enough correct types
so that the name used in the test is a prefix of the canonical name.
The big missing part is the type for the VL parameter which changes
size between rv32 and rv64.

While I was in here I noticed that we were missing some tests for
double on rv32 so I fixed that by copying from rv64 and fixing up
the VL argument type.
2020-12-30 12:37:11 -08:00
..
AArch64 Use unary CreateShuffleVector if possible 2020-12-30 22:36:08 +09:00
AMDGPU Use unary CreateShuffleVector if possible 2020-12-30 22:36:08 +09:00
ARC
ARM
AVR
BPF
Generic Use unary CreateShuffleVector if possible 2020-12-30 22:36:08 +09:00
Hexagon
Inputs
Lanai
Mips
MIR [MIRPrinter] Fix incorrect output of unnamed stack names 2020-12-28 18:01:40 +01:00
MSP430
NVPTX
PowerPC [PowerPC][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 10:32:34 -08:00
RISCV [RISCV] Cleanup some V intrinsic names used in tests to match the type overloads used. Add some missing double tests on rv32. NFC 2020-12-30 12:37:11 -08:00
SPARC
SystemZ
Thumb
Thumb2
VE
WebAssembly [WebAssembly] Prototype extending pairwise add instructions 2020-12-28 14:11:14 -08:00
WinCFGuard
WinEH
X86 [X86] Refactor AMX test case, remove unnecessary code. 2020-12-30 15:40:20 +08:00
XCore