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llvm-mirror/test/CodeGen/SystemZ/int-cmp-43.ll
Richard Sandiford b7ab6fd782 [SystemZ] Enable unaligned accesses
The code to distinguish between unaligned and aligned addresses was
already there, so this is mostly just a switch-on-and-test process.

llvm-svn: 182920
2013-05-30 09:45:42 +00:00

99 lines
2.0 KiB
LLVM

; Test 64-bit comparisons in which the second operand is a PC-relative
; variable.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@g = global i64 1
@h = global i64 1, align 4, section "foo"
; Check signed comparisons.
define i64 @f1(i64 %src1) {
; CHECK: f1:
; CHECK: cgrl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
entry:
%src2 = load i64 *@g
%cond = icmp slt i64 %src1, %src2
br i1 %cond, label %exit, label %mulb
mulb:
%mul = mul i64 %src1, %src1
br label %exit
exit:
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
ret i64 %res
}
; Check unsigned comparisons.
define i64 @f2(i64 %src1) {
; CHECK: f2:
; CHECK: clgrl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
entry:
%src2 = load i64 *@g
%cond = icmp ult i64 %src1, %src2
br i1 %cond, label %exit, label %mulb
mulb:
%mul = mul i64 %src1, %src1
br label %exit
exit:
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
ret i64 %res
}
; Check equality, which can use CRL or CLRL.
define i64 @f3(i64 %src1) {
; CHECK: f3:
; CHECK: c{{l?}}grl %r2, g
; CHECK-NEXT: je
; CHECK: br %r14
entry:
%src2 = load i64 *@g
%cond = icmp eq i64 %src1, %src2
br i1 %cond, label %exit, label %mulb
mulb:
%mul = mul i64 %src1, %src1
br label %exit
exit:
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
ret i64 %res
}
; ...likewise inequality.
define i64 @f4(i64 %src1) {
; CHECK: f4:
; CHECK: c{{l?}}grl %r2, g
; CHECK-NEXT: jlh
; CHECK: br %r14
entry:
%src2 = load i64 *@g
%cond = icmp ne i64 %src1, %src2
br i1 %cond, label %exit, label %mulb
mulb:
%mul = mul i64 %src1, %src1
br label %exit
exit:
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
ret i64 %res
}
; Repeat f1 with an unaligned address.
define i64 @f5(i64 %src1) {
; CHECK: f5:
; CHECK: larl [[REG:%r[0-5]]], h
; CHECK: cg %r2, 0([[REG]])
; CHECK-NEXT: jl
; CHECK: br %r14
entry:
%src2 = load i64 *@h, align 4
%cond = icmp slt i64 %src1, %src2
br i1 %cond, label %exit, label %mulb
mulb:
%mul = mul i64 %src1, %src1
br label %exit
exit:
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
ret i64 %res
}