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llvm-mirror/test/CodeGen
Bill Schmidt 0c245b6f0f [PPC64LE] Teach swap optimization about the doubleword splat idiom
With a previous patch, the VSX swap optimization is able to recognize
the doubleword load-splat idiom that can be implemented using lxvdsx.
However, that does not cover a doubleword splat where the source is a
register.  We can implement this using xxspltd (a special form of
xxpermdi).  This patch teaches the swap optimization pass about this
idiom.

As a prerequisite, it also permits swap optimization to succeed for
all forms of SUBREG_TO_REG.  Previously we were conservative and only
allowed SUBREG_TO_REG when it copied a full register.  However, on
reflection any form of SUBREG_TO_REG is safe in and of itself, so long
as an unsafe operation is not performed on its result.  In particular,
a widening SUBREG_TO_REG often occurs as an input to a doubleword
splat idiom, particularly in auto-vectorized code.

The doubleword splat idiom is an XXPERMDI operation where both source
registers are identical, and the selection mask is either 0 (splat the
first element) or 3 (splat the second element).  To determine whether
the registers are identical, we use the existing mechanism for looking
through "copy-like" operations.  That mechanism has a side effect of
marking the XXPERMDI operation as using a physical register, which
would invalidate its presence in a swap-optimized region.  This is
correct for the form of XXPERMDI that performs a swap and hence would
be removed, but is not what we want for a doubleword-splat variety of
XXPERMDI.  Therefore we reset the physical-register flag on the
XXPERMDI when it represents a splat.

A simple test case is added to verify that we generate the splat and
that we also remove the xxswapd instructions that would otherwise be
associated with the load and store of another operand.

llvm-svn: 241285
2015-07-02 17:03:06 +00:00
..
AArch64 [AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch also adds a function to calculate the cost of interleaved memory accesses. 2015-06-26 02:32:07 +00:00
AMDGPU Test for specific output in lit test 2015-07-01 22:34:59 +00:00
ARM ARM: add correct kill flags when combining stm instructions 2015-06-29 21:42:16 +00:00
BPF
CPP
Generic Move the personality function from LandingPadInst to Function 2015-06-17 20:52:32 +00:00
Hexagon [Hexagon] Printing packet brackets when asm printing and adding a number of tests that test packet brackets. 2015-06-18 20:43:50 +00:00
Inputs
Mips Fix "the the" in comments. 2015-06-19 01:53:21 +00:00
MIR MIR Serialization: Serialize MBB successors. 2015-06-30 18:16:42 +00:00
MSP430
NVPTX [NVPTX] expand extload/truncstore for vectors of floats 2015-07-01 21:32:42 +00:00
PowerPC [PPC64LE] Teach swap optimization about the doubleword splat idiom 2015-07-02 17:03:06 +00:00
SPARC Revert r240302 ("Bring r240130 back."). 2015-06-23 11:31:32 +00:00
SystemZ
Thumb Move the personality function from LandingPadInst to Function 2015-06-17 20:52:32 +00:00
Thumb2 ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually test for it 2015-06-24 20:03:27 +00:00
WinEH [Verifier] Verify invokes of intrinsics 2015-06-26 21:39:44 +00:00
X86 Reapply r240291: Fix shl folding in DAG combiner. 2015-07-02 11:44:54 +00:00
XCore Move the personality function from LandingPadInst to Function 2015-06-17 20:52:32 +00:00