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llvm-mirror/test/CodeGen
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Yaxun Liu ade8394717 [AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argument 
SITargetLowering::LowerCall uses dummy pointer info for byval argument, which causes
flat load instead of buffer load.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D40040

llvm-svn: 318844
2017-11-22 16:13:35 +00:00
..
AArch64 [AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects. 2017-11-21 18:08:34 +00:00
AMDGPU [AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argument 2017-11-22 16:13:35 +00:00
ARC
ARM [MI scheduler] Fix VADD and VSUB in cortex-a57 model 2017-11-21 11:01:28 +00:00
AVR [AVR] Remove the select-mbb-placement-bug.ll test 2017-11-14 04:32:49 +00:00
BPF bpf: add a test case for trunc-op optimization 2017-11-20 21:37:58 +00:00
Generic [CodeGen] Peel off the dominant case in switch statement in lowering 2017-11-14 21:44:09 +00:00
Hexagon [Hexagon] Make sure that RDF does not remove EH_LABELs 2017-11-21 21:05:51 +00:00
Inputs
Lanai MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
Mips [mips] Reorder target specific passes 2017-11-20 15:59:18 +00:00
MIR [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
MSP430
Nios2
NVPTX [NVPTX] Implement __nvvm_atom_add_gen_d builtin. 2017-11-07 22:10:54 +00:00
PowerPC [MachineCSE] Add new callback for is caller preserved or constant physregs 2017-11-20 16:55:07 +00:00
RISCV [RISCV] Use register X0 (ZERO) for constant 0 2017-11-21 08:23:08 +00:00
SPARC [Sparc] efficient pattern for UINT_TO_FP conversion 2017-11-20 22:33:58 +00:00
SystemZ [DAGCombiner] Bugfix in isAlias(). 2017-11-22 08:58:30 +00:00
Thumb [ARM] Fix incorrect conversion of a tail call to an ordinary call 2017-11-14 10:36:52 +00:00
Thumb2 [arm] Fix Unnecessary reloads from GOT. 2017-11-13 20:45:38 +00:00
WebAssembly [WebAssembly] Update cfg-stackify.ll to remove the workaround added in r318288. 2017-11-15 21:38:33 +00:00
WinEH
X86 [X86] Allow vpclmulqdq instructions to be commuted during isel to allow load folding. 2017-11-21 21:05:21 +00:00
XCore