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physical registers. This is especially critical for the later two since they start the live interval of a super-register. e.g. %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1 If this instruction is eliminated, the register scavenger will not be happy as D0 is not defined previously. This fixes PR5055. llvm-svn: 82968
20 lines
531 B
LLVM
20 lines
531 B
LLVM
; RUN: llc < %s -march=bfin -verify-machineinstrs
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; When joining live intervals of sub-registers, an MBB live-in list is not
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; updated properly. The register scavenger asserts on an undefined register.
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define i32 @foo(i8 %bar) {
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entry:
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switch i8 %bar, label %bb1203 [
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i8 117, label %bb1204
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i8 85, label %bb1204
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i8 106, label %bb1204
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]
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bb1203: ; preds = %entry
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ret i32 1
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bb1204: ; preds = %entry, %entry, %entry
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ret i32 2
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}
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