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d8d28772c9
Summary: [GlobalISel][X86] Add support for f32/f64 and vector types in RegisterBank and InstructionSelector. Reviewers: delena, zvi Reviewed By: zvi Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30533 llvm-svn: 296856
18 lines
601 B
TableGen
18 lines
601 B
TableGen
//=- X86RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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/// General Purpose Registers: RAX, RCX,...
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def GPRRegBank : RegisterBank<"GPR", [GR64]>;
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/// Floating Point/Vector Registers
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def VECRRegBank : RegisterBank<"VECR", [VR512]>;
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