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https://github.com/RPCS3/llvm-mirror.git
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239 lines
8.1 KiB
LLVM
239 lines
8.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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; RUN: llc < %s -mtriple=aarch64-eabi -mattr -neon -aarch64-neon-syntax=apple | FileCheck -check-prefix=CHECK-NONEON %s
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define i32 @cnt32_advsimd(i32 %x) nounwind readnone {
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; CHECK-LABEL: cnt32_advsimd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: fmov d0, x8
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; CHECK-NEXT: cnt.8b v0, v0
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; CHECK-NEXT: uaddlv.8b h0, v0
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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;
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; CHECK-NONEON-LABEL: cnt32_advsimd:
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; CHECK-NONEON: // %bb.0:
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; CHECK-NONEON-NEXT: lsr w8, w0, #1
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; CHECK-NONEON-NEXT: and w8, w8, #0x55555555
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; CHECK-NONEON-NEXT: sub w8, w0, w8
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; CHECK-NONEON-NEXT: and w9, w8, #0x33333333
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; CHECK-NONEON-NEXT: lsr w8, w8, #2
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; CHECK-NONEON-NEXT: and w8, w8, #0x33333333
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; CHECK-NONEON-NEXT: add w8, w9, w8
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; CHECK-NONEON-NEXT: add w8, w8, w8, lsr #4
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; CHECK-NONEON-NEXT: and w8, w8, #0xf0f0f0f
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; CHECK-NONEON-NEXT: mov w9, #16843009
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; CHECK-NONEON-NEXT: mul w8, w8, w9
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; CHECK-NONEON-NEXT: lsr w0, w8, #24
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; CHECK-NONEON-NEXT: ret
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%cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
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ret i32 %cnt
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}
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define i32 @cnt32_advsimd_2(<2 x i32> %x) {
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; CHECK-LABEL: cnt32_advsimd_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: fmov d0, x0
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; CHECK-NEXT: cnt.8b v0, v0
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; CHECK-NEXT: uaddlv.8b h0, v0
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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;
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; CHECK-NONEON-LABEL: cnt32_advsimd_2:
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; CHECK-NONEON: // %bb.0:
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; CHECK-NONEON-NEXT: lsr w8, w0, #1
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; CHECK-NONEON-NEXT: and w8, w8, #0x55555555
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; CHECK-NONEON-NEXT: sub w8, w0, w8
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; CHECK-NONEON-NEXT: and w9, w8, #0x33333333
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; CHECK-NONEON-NEXT: lsr w8, w8, #2
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; CHECK-NONEON-NEXT: and w8, w8, #0x33333333
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; CHECK-NONEON-NEXT: add w8, w9, w8
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; CHECK-NONEON-NEXT: add w8, w8, w8, lsr #4
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; CHECK-NONEON-NEXT: and w8, w8, #0xf0f0f0f
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; CHECK-NONEON-NEXT: mov w9, #16843009
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; CHECK-NONEON-NEXT: mul w8, w8, w9
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; CHECK-NONEON-NEXT: lsr w0, w8, #24
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; CHECK-NONEON-NEXT: ret
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%1 = extractelement <2 x i32> %x, i64 0
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%2 = tail call i32 @llvm.ctpop.i32(i32 %1)
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ret i32 %2
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}
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define i64 @cnt64_advsimd(i64 %x) nounwind readnone {
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; CHECK-LABEL: cnt64_advsimd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d0, x0
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; CHECK-NEXT: cnt.8b v0, v0
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; CHECK-NEXT: uaddlv.8b h0, v0
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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;
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; CHECK-NONEON-LABEL: cnt64_advsimd:
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; CHECK-NONEON: // %bb.0:
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; CHECK-NONEON-NEXT: lsr x8, x0, #1
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; CHECK-NONEON-NEXT: and x8, x8, #0x5555555555555555
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; CHECK-NONEON-NEXT: sub x8, x0, x8
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; CHECK-NONEON-NEXT: and x9, x8, #0x3333333333333333
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; CHECK-NONEON-NEXT: lsr x8, x8, #2
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; CHECK-NONEON-NEXT: and x8, x8, #0x3333333333333333
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; CHECK-NONEON-NEXT: add x8, x9, x8
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; CHECK-NONEON-NEXT: add x8, x8, x8, lsr #4
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; CHECK-NONEON-NEXT: and x8, x8, #0xf0f0f0f0f0f0f0f
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; CHECK-NONEON-NEXT: mov x9, #72340172838076673
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; CHECK-NONEON-NEXT: mul x8, x8, x9
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; CHECK-NONEON-NEXT: lsr x0, x8, #56
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; CHECK-NONEON-NEXT: ret
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%cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
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ret i64 %cnt
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}
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; Do not use AdvSIMD when -mno-implicit-float is specified.
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; rdar://9473858
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define i32 @cnt32(i32 %x) nounwind readnone noimplicitfloat {
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; CHECK-LABEL: cnt32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w8, w0, #1
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; CHECK-NEXT: and w8, w8, #0x55555555
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; CHECK-NEXT: sub w8, w0, w8
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; CHECK-NEXT: and w9, w8, #0x33333333
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; CHECK-NEXT: lsr w8, w8, #2
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; CHECK-NEXT: and w8, w8, #0x33333333
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; CHECK-NEXT: add w8, w9, w8
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; CHECK-NEXT: add w8, w8, w8, lsr #4
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; CHECK-NEXT: and w8, w8, #0xf0f0f0f
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; CHECK-NEXT: mov w9, #16843009
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; CHECK-NEXT: mul w8, w8, w9
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; CHECK-NEXT: lsr w0, w8, #24
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; CHECK-NEXT: ret
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;
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; CHECK-NONEON-LABEL: cnt32:
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; CHECK-NONEON: // %bb.0:
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; CHECK-NONEON-NEXT: lsr w8, w0, #1
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; CHECK-NONEON-NEXT: and w8, w8, #0x55555555
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; CHECK-NONEON-NEXT: sub w8, w0, w8
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; CHECK-NONEON-NEXT: and w9, w8, #0x33333333
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; CHECK-NONEON-NEXT: lsr w8, w8, #2
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; CHECK-NONEON-NEXT: and w8, w8, #0x33333333
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; CHECK-NONEON-NEXT: add w8, w9, w8
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; CHECK-NONEON-NEXT: add w8, w8, w8, lsr #4
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; CHECK-NONEON-NEXT: and w8, w8, #0xf0f0f0f
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; CHECK-NONEON-NEXT: mov w9, #16843009
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; CHECK-NONEON-NEXT: mul w8, w8, w9
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; CHECK-NONEON-NEXT: lsr w0, w8, #24
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; CHECK-NONEON-NEXT: ret
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%cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
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ret i32 %cnt
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}
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define i64 @cnt64(i64 %x) nounwind readnone noimplicitfloat {
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; CHECK-LABEL: cnt64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, #1
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; CHECK-NEXT: and x8, x8, #0x5555555555555555
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; CHECK-NEXT: sub x8, x0, x8
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; CHECK-NEXT: and x9, x8, #0x3333333333333333
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; CHECK-NEXT: lsr x8, x8, #2
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; CHECK-NEXT: and x8, x8, #0x3333333333333333
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; CHECK-NEXT: add x8, x9, x8
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; CHECK-NEXT: add x8, x8, x8, lsr #4
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; CHECK-NEXT: and x8, x8, #0xf0f0f0f0f0f0f0f
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; CHECK-NEXT: mov x9, #72340172838076673
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; CHECK-NEXT: mul x8, x8, x9
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; CHECK-NEXT: lsr x0, x8, #56
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; CHECK-NEXT: ret
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;
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; CHECK-NONEON-LABEL: cnt64:
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; CHECK-NONEON: // %bb.0:
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; CHECK-NONEON-NEXT: lsr x8, x0, #1
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; CHECK-NONEON-NEXT: and x8, x8, #0x5555555555555555
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; CHECK-NONEON-NEXT: sub x8, x0, x8
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; CHECK-NONEON-NEXT: and x9, x8, #0x3333333333333333
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; CHECK-NONEON-NEXT: lsr x8, x8, #2
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; CHECK-NONEON-NEXT: and x8, x8, #0x3333333333333333
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; CHECK-NONEON-NEXT: add x8, x9, x8
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; CHECK-NONEON-NEXT: add x8, x8, x8, lsr #4
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; CHECK-NONEON-NEXT: and x8, x8, #0xf0f0f0f0f0f0f0f
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; CHECK-NONEON-NEXT: mov x9, #72340172838076673
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; CHECK-NONEON-NEXT: mul x8, x8, x9
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; CHECK-NONEON-NEXT: lsr x0, x8, #56
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; CHECK-NONEON-NEXT: ret
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%cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
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ret i64 %cnt
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}
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define i32 @ctpop_eq_one(i64 %x) nounwind readnone {
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; CHECK-LABEL: ctpop_eq_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d0, x0
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; CHECK-NEXT: cnt.8b v0, v0
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; CHECK-NEXT: uaddlv.8b h0, v0
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: cmp x8, #1 // =1
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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;
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; CHECK-NONEON-LABEL: ctpop_eq_one:
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; CHECK-NONEON: // %bb.0:
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; CHECK-NONEON-NEXT: lsr x8, x0, #1
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; CHECK-NONEON-NEXT: and x8, x8, #0x5555555555555555
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; CHECK-NONEON-NEXT: sub x8, x0, x8
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; CHECK-NONEON-NEXT: and x9, x8, #0x3333333333333333
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; CHECK-NONEON-NEXT: lsr x8, x8, #2
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; CHECK-NONEON-NEXT: and x8, x8, #0x3333333333333333
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; CHECK-NONEON-NEXT: add x8, x9, x8
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; CHECK-NONEON-NEXT: add x8, x8, x8, lsr #4
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; CHECK-NONEON-NEXT: and x8, x8, #0xf0f0f0f0f0f0f0f
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; CHECK-NONEON-NEXT: mov x9, #72340172838076673
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; CHECK-NONEON-NEXT: mul x8, x8, x9
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; CHECK-NONEON-NEXT: lsr x8, x8, #56
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; CHECK-NONEON-NEXT: cmp x8, #1 // =1
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; CHECK-NONEON-NEXT: cset w0, eq
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; CHECK-NONEON-NEXT: ret
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%count = tail call i64 @llvm.ctpop.i64(i64 %x)
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%cmp = icmp eq i64 %count, 1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @ctpop_ne_one(i64 %x) nounwind readnone {
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; CHECK-LABEL: ctpop_ne_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d0, x0
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; CHECK-NEXT: cnt.8b v0, v0
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; CHECK-NEXT: uaddlv.8b h0, v0
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: cmp x8, #1 // =1
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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;
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; CHECK-NONEON-LABEL: ctpop_ne_one:
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; CHECK-NONEON: // %bb.0:
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; CHECK-NONEON-NEXT: lsr x8, x0, #1
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; CHECK-NONEON-NEXT: and x8, x8, #0x5555555555555555
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; CHECK-NONEON-NEXT: sub x8, x0, x8
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; CHECK-NONEON-NEXT: and x9, x8, #0x3333333333333333
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; CHECK-NONEON-NEXT: lsr x8, x8, #2
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; CHECK-NONEON-NEXT: and x8, x8, #0x3333333333333333
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; CHECK-NONEON-NEXT: add x8, x9, x8
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; CHECK-NONEON-NEXT: add x8, x8, x8, lsr #4
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; CHECK-NONEON-NEXT: and x8, x8, #0xf0f0f0f0f0f0f0f
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; CHECK-NONEON-NEXT: mov x9, #72340172838076673
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; CHECK-NONEON-NEXT: mul x8, x8, x9
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; CHECK-NONEON-NEXT: lsr x8, x8, #56
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; CHECK-NONEON-NEXT: cmp x8, #1 // =1
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; CHECK-NONEON-NEXT: cset w0, ne
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; CHECK-NONEON-NEXT: ret
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%count = tail call i64 @llvm.ctpop.i64(i64 %x)
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%cmp = icmp ne i64 %count, 1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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