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8fc47f8652
For these cases, we already omit the prologue directives, if (!AFI->hasStackFrame() && !windowsRequiresStackProbe && !NumBytes). When writing the epilogue (after the prolog has been written), if the function doesn't have the WinCFI flag set (i.e. if no prologue was generated), assume that no epilogue will be needed either, and don't emit any epilog start pseudo instruction. After completing the epilogue, make sure that it actually matched the prologue. Previously, when epilogue start/end was generated, but no prologue, the unwind info for such functions actually was huge; 12 bytes xdata (4 bytes header, 4 bytes for one non-folded epilogue header, 4 bytes for padded opcodes) and 8 bytes pdata. Because the epilog consisted of one opcode (end) but the prolog was empty (no .seh_endprologue), the epilogue couldn't be folded into the prologue, and thus couldn't be considered for packed form either. On a 6.5 MB DLL with 110 KB pdata and 166 KB xdata, this gets rid of 38 KB pdata and 62 KB xdata. Differential Revision: https://reviews.llvm.org/D88641
49 lines
1.3 KiB
LLVM
49 lines
1.3 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
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; CHECK-LABEL: testmsxs:
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; CHECK: frintx [[SREG:s[0-9]+]], s0
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; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]]
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; CHECK-NEXT: sxtw x0, [[WREG]]
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; CHECK-NEXT: ret
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define i64 @testmsxs(float %x) {
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entry:
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%0 = tail call i32 @llvm.lrint.i32.f32(float %x)
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%conv = sext i32 %0 to i64
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ret i64 %conv
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}
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; CHECK-LABEL: testmsws:
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; CHECK: frintx [[SREG:s[0-9]+]], s0
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; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]]
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; CHECK-NEXT: ret
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define i32 @testmsws(float %x) {
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entry:
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%0 = tail call i32 @llvm.lrint.i32.f32(float %x)
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ret i32 %0
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}
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; CHECK-LABEL: testmsxd:
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; CHECK: frintx [[DREG:d[0-9]+]], d0
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; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]]
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; CHECK-NEXT: sxtw x0, [[WREG]]
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; CHECK-NEXT: ret
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define i64 @testmsxd(double %x) {
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entry:
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%0 = tail call i32 @llvm.lrint.i32.f64(double %x)
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%conv = sext i32 %0 to i64
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ret i64 %conv
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}
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; CHECK-LABEL: testmswd:
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; CHECK: frintx [[DREG:d[0-9]+]], d0
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; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]]
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; CHECK-NEXT: ret
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define i32 @testmswd(double %x) {
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entry:
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%0 = tail call i32 @llvm.lrint.i32.f64(double %x)
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ret i32 %0
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}
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declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
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declare i32 @llvm.lrint.i32.f64(double) nounwind readnone
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